Hi,

As far as I know the mismatch parameter for Monte Carlo is assuming that the device is place side by side. If the transistors in the layout is being matched carefully, the Monte Carlo might over estimate the mismatch. In spectre, you can set the correlation ranging from 0 to 0.99 and it is affecting my simulation results. Did you set your Monte Carlo simulation to simulate mismatch? I was doing that to find out the offset voltage for an OPAMP and it works fine for me.

Regards,
Chase

Hi,

the correlation to be set depends on the mismatch parameters in your model. In most cases, these are extracted for nearby matched devices (same orientation, shape and size etc.). In that case, the correlation effect is already taken care of in the parameters and MC would underestimate mismatch for distant or badly matched devices. If I remember correctly, correlation > 0 lowers the effectively applied mismatch between two devices, so a high correlation parameter (i.e. close to 1) may result in underestimated offset results.

The electrical parameter manual coming with the device models should contain information on the assumptions made during the mismatch parameter extraction and the use of the correlation parameter.

Paul

Jet_Wu wrote on Apr 21^st, 2006, 10:42am:


Monte Carlo doesn't overestimate.  Believe it or not, poor layout techniques don't affect the variance (or standard deviation) of Vt mismatch much, at least not on a single wafer were matching parameters would be measured.  I've even seen matching between devices with a 90 degree rotation and the difference is small (I think the mobility mismatch does increase, however, and different lots may produce different mean values).  What happens is an unpredictable systematic offset is introduced, so it is obviously a bad idea to use "unmatched layouts."

Anyway, generally you can assume that using common centroid layouts, dummy devices, etc, won't buy you much in terms of reduced standard deviation, but it will properly center your design.

Paul, I think yer bored and needed something to post :-).  I was worried that people might get the idea that common centroids weren't needed so I mentioned that they were useful not once, but twice.  I was going to mention thermal gradients, but it just seemed to be getting more off topic to give yet another reason.  By the way, you forgot temperature dependent stess, esp. in plastic packages. ;)

The main point was to answer the question, and to give the reason why.  Monte Carlo isn't pessimistic; you shouldn't expect common centroid to decrease the random offsets caused by device mismatch - that is just an oft repeated myth.    

Anyway, are you sure you didn't mean V_T mismatch in the post below?  The effect of mobility mismatch in a diff pair is minimized by biasing in weak inversion, whereas the effects of V_T mismatch is bias independent (for a diff pair).

Paul wrote on Apr 29^th, 2006, 5:56am:

Hi Paul, Rob,

I would like to add one comment to the discussion:

While it is true that current mirror mismatch in strong inversion depends on mobility mismatch,
the level of inversion required to attain the state where mobility mismatch dominates over VT
mismatch may be quite high, high enough that one never encounters it.

Perhaps this is a process dependent thing, but I remember doing a calculation long ago with one of
the processes I was using, and with information about VT mismatch and mobility mismatch based
on measurements of well-matched devices, I found that the (VGS-VT) level needed to be about 2x
the maximum operating VGS allowed in the process.

So for all practical purposes, mobility mismatch was negligible. I would advice everyone to
first write out a simple equation for estimating the sensitivity (dI/I) based on VT and mobility
mismatch values, and to plug in the numbers from their respective process docs to see the dominant
source of mismatch.

I typically allow  >= 1V (VGS-VT) and use long channel devices in a 3.3V process for realizing current
mirrors, wherever possible.

Regards
Vivek