I wonder how to determine the input common voltage of a simple 5 MOS transistors differential amplifier.For example, assume two NMOS's as the differential input pair with the PMOS's configured as active loads. I try DC sweep to find the skewest point of the transfer curve, but at that point, the CMRR is low too. Anybody help? Thanks!

Hi,

as Raul already mentioned, the input CM range is delimited by the voltage levels, where one of the devices goes out of saturation. For lower input CM, it is the current source which will enter triode region, on the upper end it may either be the diff pair or the active loads. If you have a differential output, this will depend on your output CM setting.

Plotting the DC open-loop gain while sweeping the input CM should reveal both limits. Is this what you describe in your post? I don't exactly understand what operating point you select. In any case, in the middle of the obtained range, the gain should be maximum and the CMRR should be good. Don't go to close to either border in the typical case as this value somewhat varies with the transistor's threshold voltages.

Paul

Hi,

there are two issues in the way you run your simulation.
1) If you want to have a fully differential output, you must use common-mode feedback (CMFB) to regulate the pbias voltage. You cannot apply fixed current levels on either side of the diff pair, otherwise one of the current sources must go into triode region to compensate for the current mismatch.
2) The voltage gain is given by vout_diff/vin_diff, not by vout_p(n)/vi_cm as you plot it. In the presented graph, you obtain the input level for which the tail current becomes larger than the PMOS current. In order to plot the voltage gain, you must run an AC simulation with an AC differential input signal and plot vout_diff/vin_diff. Then you combine this AC simulation with a DC sweep of the CM voltage.

Does this answer your question?

Paul