Here is a writeup on designing ESD protection that I did for one of the magazines:-- schematic is in the attachement --
Circuits for Electro-Static Discharge Protection
Designing for Amps of Current Equals Kilovolts of ESD Protection Jerry Twomey
www.effectiveelectrons.comWhen presented with the subject of ESD circuits, many designers run the other way. Kilovolts applied to a transistor that normally functions with less than a volt applied? How do they do that? Let’s take a look at what happens in an ESD event and see how to create the circuits to deal with it.
The figure shows a typical test case and the associated circuits. CESD, RHBM, and SW1 provide a circuit model to represent the ESD stimulus. RHBM is 1500 ohms in order to represent the Human Body Model (HBM) or is set to 0 ohms to represent the Machine Model (MM) situation. The JEDEC standard for ESD testing sets CESD to 100pf for the HBM, and 200pf for the MM. Polarity of VESD can be either positive or negative.
Visualization of ESD events needs to consider that the chip is not yet soldered to a PCB, or may still be an unpackaged die. Consequently, the static voltage applied to the input pin needs to be modeled without power supplies, or any external circuitry. The primary issue is limiting the resulting VGate relative to Vpower and VBulk, the internal bulk ground. Protecting the MOS gate oxide is what this is all about.
When the switch closes, the initial current surge due to VESD is largely defined by the RHBM for the HBM case, and by the equivalent series resistance of a forward biased diode for the MM case. The combination of these defines the VGate potential.
A negative ESD event is fairly straightforward, VESD is negative, the switch closes, and VGate gets pulled below VBulk, providing forward bias for D2. This leads to a high initial current surge, which can peak in multiple amperes. This becomes the defining issue in ESD circuit effectiveness. For the negative event, the series resistance inherent to both diode and the connection paths determines the magnitude of VGate.
The high currents require careful modeling of everything in the series path impedance associated with the diode. The voltage that appears at VGate becomes an exercise in high current voltage division. SPICE tools can be used to provide an approximate simulation of the ESD circuit and how it responds. However, the diode model needs to be valid for high currents to be meaningful. Ideal diodes presented in some design kit configurations are invalid at high currents.
The positive ESD event is a little different. VESD is positive, and when SW1 closes, VGate rises above Vpower and D1 is forward biased. A high voltage again needs to be avoided at Vgate and thus a low impedance return path is needed. This is done by providing a switched clamp between Vpower and VBulk, through which the high current return path is created. The clamp also sees amps of current and needs appropriate models.
The architecture of the clamp can be as simple as an NMOS switch, which detects a large dv/dt event, or various SCR type devices are also available on a CMOS process. For fabless design groups, the NMOS works reasonably well, and does not require the model and layout development needed for the SCR’s.
Special layout considerations include:
• Low resistance, heavily contacted diode structures
• Low resistance, high current metal interconnects for signals
• Oversized geometry on components due to currents.
• Perimeter substrate contacts closely placed around substrate-based structures
• Perimeter well tie ups closely placed around well-based structures
• High current grounding and tie up connection paths
Special considerations for simulation and modeling include:
• Accurate diode models for high currents.
• Simulation error tolerances configured to allow kilovolts and millivolts at the same time
• Test benches representing the chip in “not yet soldered down” situations.
• ESD needs to function for both packaged and unpackaged devices.
Conclusions
Basic ESD circuits are within the capability of any transistor level designer. Although a lot of pre-fabricated ESD circuits are available in I/O cells, the need often arises for custom I/O’s to suit special needs. Also, ESD circuits consume the most area in I/O circuits, and custom designs can reduce overall chip size. Concentrating on the high current aspects of the problem allows successful design, and this can be especially valuable in space constrained chips.
References:
Available at
www.jedec.orgJedec Standard 22-A114-B – Human Body Model for ESD Testing
Jedec Test Method A115-B – Machine Model for ESD Testing
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