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Timestep control in NCsim (Read 3378 times)
Dave Dobson
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Kanata, Ontario, CA
Timestep control in NCsim
May 02nd, 2006, 12:51pm
 
What governs the timestep selection in ncsim?
In my analog process, I have a clock source with a 100ps period. This clock is then divided by 2 and then divided by 2 again. The digital process generates a serial data stream with a 100ps bit period. This data stream goes through a connect module into the analog block and is processed.

The timescale in the connect module is 1ps/1ps. I have the spectre errpreset=liberal (I have also tried moderate with the same results as described below).

When I simulate with ncsim, I see that when the serial data stream contains no transitions, the analog clocks also have no transitions. This is not what I expected. I expected that the analog process would set the timestep of ncsim and that the maximum timestep would be something less than 100ps, in order to reproduce the highest frequency clock. Instead, it seems that the digital process is dictating the timestep of the analog process. When there are transitions in the serial data stream, then I can see transitions of the correct period for the analog clocks.

I am concerned that the resolution of the analog model will be compromised with the digital process imposing a timestep.
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jbdavid
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Silicon Valley
Re: Timestep control in NCsim
Reply #1 - Aug 11th, 2006, 2:18am
 
If there is no event passing from the digital side to the analog side, WHY would you want your analog simulation to slow down?

If you are using a
Code:
reg Da = 0;
always @(posedge Din) Da = 1;
always @(negedge Din) Da = 0;
analog V(Aout) <+ Vdd*transition(Da,td,tr,tf);  


you'll force at least two timesteps after each transition,
one at $abstime+td
and the other at
$abstime + td+ tr (rising edge)
$abstime + td+ tf (falling edge)

but if there is no event, there need be no analog time steps..
so your simulation is done faster.
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jbdavid
Mixed Signal Design Verification
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