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Verilog A (Read 2987 times)

Jamz_will New Member Offline Posts: 6 Singapore	Verilog A Aug 14^th, 2006, 6:31pm Hi, Can I simulate my spice netlist and verilog behavioral model using verilog -a simulator if they behave the same? If its possible, can you give me an idea how? Thanks. Jamz_will
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Geoffrey_Coram

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Massachusetts, USA

Re: Verilog A
Reply #1 - Aug 15^th, 2006, 4:38am

Most if not all of the major analog simulators support Verilog-A. You can either run two netlists (one Verilog-A, one transistor-level) and compare the output waveforms from two simulations, or you can try to merge the two netlists into one (eg, put "adder" and "adder_va" in one netlist, and hook up their inputs to the same voltage sources, or if you have current inputs, you probably need to duplicate them) and compare the outputs within one simulation.

If at first you do succeed, STOP, raise your standards, and stop wasting your time.

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Ken Kundert Global Moderator Offline Posts: 2384 Silicon Valley	Re: Verilog A Reply #2 - Aug 15^th, 2006, 8:38am You cannot simulate Verilog code in a Verilog-A simulator. Verilog-A is a Verilog-like language suitable for describing analog circuitry. If you have Verilog code, you will need a Verilog-AMS simulator, which combines Verilog and Verilog-A. Verilog-AMS simulators allow one to combine SPICE netlists with Verilog code. -Ken
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