Hi Gary,

Worst-case speed has nothing to do with mismatch. It typically implies high transistor VT, and low mobility.

Regards
Vivek

vivkr wrote on May 8^th, 2006, 3:20am:


And high temperature as well

* Referring to last comment about temperature:
The Vt of CMOS transistor decreases as temparature increases, So in worst case for speed, one has to combine lowest temperature with low speed corner (high Vt).

Hamed

I can't agree with that. The degradation of mobility with growing temperature is going much faster then reduction of Vt.
So, use SS process corner, the lowerst supply voltage and the highest possible junction temperature

Take ring oscillator of 7 invertors and check the frequency as a function of temperature in TRAN simulation and won't be surprized.

Ok. I am designing CMOS analog during last 11 years, and according to my experience, high temperature increases delays. I just did the simulation, I suggested in my previous post. Ring oscillator, 7 inverters, 0.13 u process from very respectable FAB, model: BSIM3v3, supply 1.2V and 3 different TEMP 25, 70 and 125.
No parasitics, ideal supply.
The slowest corresponds to 125 deg C.

Hello everybody,

I agree with mikki33 as well. Please note that the degradation of mobility depends on the movement of the crystalline lattice.

Regards,

fran2k5

hamed wrote on Jun 14^th, 2006, 6:23am:


Hi Hamed,

I would be wary of making a statement like that. The most important parameter in analog design is arguably the transconductance (Gm) of the device. In fact, even in digital circuits, which are analog in reality, the same holds equally true.

And Gm depends first on mobility of the device (Kn'= un*Cox). Vth is a composite of several quantities, and ideally ought not to influence the speed. However, a larger Vth implies a higher overdrive to achieve the same Gm in the device. So both un and Vth are instrumental here.
The fundamental speed of the device is proportional to un/L, and hence shorter channels offer higher speed due to reduced transit time.

Please keep in mind the following:

1. Vth variation across process is strongly dependent on doping and oxide contamination as far as I know (Vth here implies threshold voltage).

2. If wafer A and B have the same un (mobility) & Cox & L but differ only in Vth, then the wafer with the larger Vth is the slower one. However, Vth alone cannot provide speed information.

3. Given a wafer, the speed will typically reduce with temperature despite the reduction in Vth at higher temperature. This is due to the fact that the mobility reduction due to higher temperatures has a stronger impact on speed than Vth reduction. Hence, the worst-speed situation is for worst-speed process (highest Vth, lowest Kn') and highest temperature with lowest supply.

4. Thus, the worst-speed corner assumes lowest un, highest Vth, and also longest L (in good process models).

5. Perhaps there are some special circuits which behave a bit differently, but in general the device transit time should increase as the temperature goes up, and this is the fundamental criteria for testing the speed of a device.

Regards
Vivek