Faisal
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Hi,
I am running DRC, LVS checks with Diva on my blocks and it indicates that there are no errors. I then do my post layout simulation with analog extracted netlist and the results are correct. However when I run DRACULA on the chip level, I find many errors e.g. unmatched device, unmatched node etc
What could be the possible reasons ?? Which tool is more trust worthy ?? Is this safe for tapeout ??
Regards, Faisal
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