does the hierarchy editor (config view) pick up the verilog hierarchy ? it should list the verilog sub modules.

If this is not the case then this must be corrected. I haven't used spectreVerilog in a while, and as I am an analogue person, I guess I would create symbol and functional views for all the bits of verilog code in dfII format (cellname->viewname), then i think the config view will pick them up nicely.
To create the dfII format cellname->functional, I would use create cellview using verilog-editor in dfII to ensure the parser and auto-symbol generation are invoked. That way you'll know if you have any verilog code which the somewhat old verilogXL executable linked to in spectreVerilog doesn't like.

cheers

aw

Hi,

Thank you for your reply. I actually fixed the problem after talking to a few groupmates of mine who were not in the lab last night. Here is the solution.
The hiererchy editor does not recognize the instantiated cells in a Verilog code (at least it did not do it in mine). I had to set the directory where the modules I instantiated were located manually. After opening Analog Environment, choose SpectreVerilog as the simulator. Then, go to Simulation -> Options -> Digital and write the path to your library in the "Library Directories". That will take care of the problems. Make sure, if you are instantiating any standard cells, you should add the path to that standard cell library as well. You might like to include some library files as well.