Does your system have a lot of Ls?  They add an extra matrix row to the set of equations, so this could be an issue for large circuits -- though I doubt you'd notice it in a small circuit.

It's also possible that the equations are scaled differently in Verilog-A than with the Ls and Cs, such that the tolerances are harder to satisfy one way or another; ie, if you have a time constant sqrt(1/(LC))  you could get the same constant by doubling L and halving C, but the current in the inductor would be changed by a factor of two and thus the circuit might take fewer iterations to converge (current error less than abstol).