schehrazi
Community Member
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Posts: 45
University of CA, LA
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Hi,
Thank you for your reply. I actually fixed the problem after talking to a few groupmates of mine who were not in the lab last night. Here is the solution. The hiererchy editor does not recognize the instantiated cells in a Verilog code (at least it did not do it in mine). I had to set the directory where the modules I instantiated were located manually. After opening Analog Environment, choose SpectreVerilog as the simulator. Then, go to Simulation -> Options -> Digital and write the path to your library in the "Library Directories". That will take care of the problems. Make sure, if you are instantiating any standard cells, you should add the path to that standard cell library as well. You might like to include some library files as well.
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