NKS
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Posts: 7
Seoul, Korea
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Does anyone know how stable the model described in the paper is? I've been coding a Verilog-a code based on the outline described in the paper for some time, now. So far, I have been able to make it exhibit the snapback phenomenon for ggNMOS (Vgs=0) case as shown in the figure below. However, I was only able to get to this point per lots of parameter tweaking. Without tweaking, a simulation run generally ends up in convergence error as shown in the same figure for Vgs=0.5V case.
Upon reading the paper, I got the impression that the equations shown in the paper do not induce severe convergence problems. What common mistakes would I be making?
Specifically I have following questions:
1. What are the values for the parameters that would result in reasonably similar results as the plots shown in the paper; I've tried to contact one of the authors about this matter but did not receive any response. For example, p1, p2, p3, A, B, I_oc, Iob, R_sub, R_on, C_GD, C_Db, C_GS, C_Sb, C_Gb, Tox, Mu_eff. 2. Do I need to check some condition(ex. voltages across some nodes) before executing the equations in Table II? 3. How good (low convergence error occurence and reasonable precision) is this approach of behavior modeling ESD devices? Is the difficulty with simulation convergence inevitable with this kind of approach? Or am I missing some subtilties with my coding.
Thanks in advance.
NKS :(
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