mikki33 wrote on Jun 11th, 2006, 9:08am:I think I can help, but I didn't understand the question...
I figured that would happen...
My apologies!
Here's a pic of the situation. I don't get why the load line for Z0 gives a current of Vdd/Z0 when Vds=0. This kind of makes sense if you think of Z0 as a resistor with the far end at Vdd. This way, if the drain end is 0, you get Vdd/Z0 is the current sunk by the NMOS. The things I don't get are how you can have a current with an open termination (it should be zero when things settle out). In other words, I don't get how that load line works. (It would make sense to me if it was depicting a common source amplifier with a resistor load).
The point of the curve is to find out if your MOSFET is sized correctly to generate a Vdd/2 wave when turned on.
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My understanding of the transmission is that a positive voltage wave of Vdd/2 is launched, and the current is being sunk by the MOSFET. Since it's an open termination, the current must become zero. To accomplish this, a wave of zero volts is setup at the far end, which causes a current in the opposite direction. This zero volt wave comes back to the drain (near end) and the voltage goes from Vdd/2 to zero. Is this the right way to think about how the current becomes zero?
Thanks,
Marc