I'm studying I/O and I'm a bit confused about the CMOS I/O scheme.  It is series terminated by the resistances of the N or PMOS.  

In one book they draw a load line for the transmission line along with the NMOS I vs. Vds curve for Vgs=Vdd.  The load line is the same as you would get if you had a load of Z0 in a common source amp (a straight line with I=Vdd/Z0 @ Vds=0 and I=0 @ Vds=Vdd).  Certainly I understand this for a CS amp, but not for the transmission line.

My issue is that I don't see how you get a current of Vdd/Z0 when the voltage at the NMOS end of the line is 0.  For this line, aren't the reflections always supposed to make the current zero, since it is an open-ended line?  How do they get the load line for the trans. line to be the same as a resistive load with one end connected to Vdd?

Oh, the goal of doing the load line is to find the point where the NMOS drain output is Vdd/2 when Vgs=Vdd.  The idea is to launch a Vdd/2 wave and then have the reflection come back and make Vds=0.

Thanks,
Marc

mikki33 wrote on Jun 11^th, 2006, 9:08am:


I figured that would happen...  My apologies!

Here's a pic of the situation.  I don't get why the load line for Z0 gives a current of Vdd/Z0 when Vds=0.  This kind of makes sense if you think of Z0 as a resistor with the far end at Vdd.  This way, if the drain end is 0, you get Vdd/Z0 is the current sunk by the NMOS.  The things I don't get are how you can have a current with an open termination (it should be zero when things settle out).  In other words, I don't get how that load line works.  (It would make sense to me if it was depicting a common source amplifier with a resistor load).

The point of the curve is to find out if your MOSFET is sized correctly to generate a Vdd/2 wave when turned on.


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My understanding of the transmission is that a positive voltage wave of Vdd/2 is launched, and the current is being sunk by the MOSFET.  Since it's an open termination, the current must become zero.  To accomplish this, a wave of zero volts is setup at the far end, which causes a current in the opposite direction.  This zero volt wave comes back to the drain (near end) and the voltage goes from Vdd/2 to zero.  Is this the right way to think about how the current becomes zero?

Thanks,
Marc

Marc, you are right it is confusing. Especially I can't understand how to combine Z0 and DC opereting point.
Do you consider the source of this knowledge to be reliable?

I would first separate DC and AC parts. For the DC operating point the graph you posted is probable. But, in this case, Z0 becomes R0. And if it is connected to VDD, you are getting load line like on the graph.

For AC, it is not so clear. What kind of signal the author is talking about small or large one (Z0???). What is the termination at the far end? What is the AC ground (virtual voltage of VDD/2???)? Etc. Etc. Etc.

May be the best thing is to read another book or article?
Try to find "A Self-Terminating Low-Voltage Swing CMOS Output Driver" (IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL. 23,NO 2,APRIL 1988). This is the very beginning of the high speed I/O.

(If you can't find it, you may leave me your e-mail in PM, I can send the article to you.)

Hope, this helps,
Michael

So, they probably ment:

No, it is open ended from AC point of view. For the DC you have to define operation point...
So, I can think about other possibilities

The essential part of this circuit that R_on of the NMOS transistor equals to the |Z0|. This makes perfect termination. Therefore, you have to plot I_ds and 1/Z0 and find the point of their intersection.

At least make sense.