Hi Marc,

I've been trying to make substrate analysis a standard part of my design process and considered early when it can make the most difference so this is a work in progress to this end.

Now, the approach that was laid out is to help handle floor planning and isolation before layout is done. Once layout is done there are tools available to help do a more accurate extraction of your substrate. This analysis might not be necessary after layout and extraction but because the extraction tools make a large simulation problem even larger the ideas may be needed to help reduce the coupling problem to an understandable level. It is often beneficial and/or necessary to reduce the extracted network and simulation down to the critical elements and I hope the analysis approach helps to highlight the critical areas and elements to consider.

In regard to the 50um separation compared to the 300um thickness, I am referring to the likely direction and strength of the electrical fields. If the substrate was thin and backside grounded then we would expect a large amount of the fields to go to the backside ground. This would be good since most of our aggressor signal would terminate to the back side ground before traveling far horizontally to another circuit. Thinning the die down is an option to improve isolation with some assembly and manufacturing limitations. If the substrate is thick and a surface ground contact is relatively close to the signal generator then we'd see strong fields flowing to the surface ground which is what I assume. The surface current assumption helps to simplify the coupling behavior for our analysis. There is a loss in accuracy so the post-layout substrate extract is needed for accuracy but this simplification allows us to do some analysis early.

When it discussed "closely spaced guardrings" it is simply referring to spacing between any other guardring. This assumption is again focusing on fields coupling to the next nearest conductor. If electrical fields tend to flow to the next nearest surface conductor and that the edges of the guardring are wide compared to the separation then the fields will largely be contained between two near edges. This allows us to focus on one edge at a time. This also allows us to place a single resistance to model this coupling between any two adjacent edges. For a rectangular guardring surrounded on all four sides by other guardrings we would place one resistor per side to model the coupling between each side to the next adjacent guardring. In this way we can build up a network of conducting rings with resistors between the edges of adjacent rings. I have run EM simulations of various ring widths and separations and compared with a single wire with the length equal to the ring edge width being considered and the coupling was <2dB different, meaning that the simplification of handling each edge by itself is <2dB different than considering the whole ring.

The R values are the next part of the analysis and the real missing piece of early substrate modeling. I hope to publish my results later but for now I'll explain what I have done to determine these R values. Again we are relying on EM simulation or other substrate tool to determine our coupling but with some of the previous observations we can extract out lumped element models from the simulation results. I've taken two guardrings placed adjacent to each other with a spacing (S) and edge width (W) and then surrounded all other edges of both guardings by ground planes also separated by spacing (S). The adjacent edges of the guardring are made into Port1 and Port2 and simulated to generate the two-port S-parameters. This can be analyzed and a pi network can be extracted with resistance down to the backside ground and resistance between the ports. If we consider the whole circuit area to be a sea of substrate contacts then we can model this as a single large parallel plate over the backside ground and it has a low resistance to ground. The guardring shows higher resistance to the backside ground and less resistance to the adjacent guardring because it doesn't have much surface area and is far from the backside ground but the adjacent ring is close in comparison. From various (S) and (W) value simulations I've extracted out a scalable resistance value for my process for edge-to-edge resistance and a plate resistance for (WxW) to backside ground. The scalable resistance allows us to make early assumptions about (S) and a nominal (W) and circuit/chip designers can include this in their design flow without having to spend time doing layout and extraction just to get an estimate.

I hope this helps to explain the process and I hope to publish how to extract out resistance parameters sometime soon.

Best regards,

- Glenn Murata

Is substrate current caused primarily by impact ionization (for NMOS, e-h pairs get created and holes enter the substrate)?  Then there is also the p-n junction reverse current, right?

Are those the only 2 important sources of substrate current?

Thanks,
Marc

Ah yes, I was aware of this but it slipped my mind when posing the question...was thinking about the device physics!  

While I'm here, I want to check my understanding.

So, you are talking about IR drop through the metal which causes a difference in voltage between substrate contacts.  Let's say I have substrate contacts on opposite sides of the chip both connected by a metal1 line to ground.  If current through metal1 is low such that there is not much of an IR drop.  there should be no difference in voltage and thus no substrate current, right?  

However, if I had a MOSFET in the center of the chip, it would still be injecting substrate current due to impact ionization and reverse leakage, right?  This current would have to find it's way to the substrate contact via the substrate and thus encounter a lot of substrate resistance, right?  Because the current flows through a large resistance, there is enough of a voltage drop to activate the parasitic BJTs and cause latch up, right?

In this situation, to fix the problem, I would have to put a substrate contact (connected to ground and the other substrate contacts via metal1) in the center of the chip next to the MOSFET.  This contact would give the substrate current a path to get to ground via the metal1 line and thus avoid causing a voltage drop in the substrate, right?

In the case where I have a high IR drop on the metal1 line, does adding more substrate contacts help?  There would still be a voltage drop between the contacts and thus substrate current flow would occur.  It seems like making the metal1 wider would be the solution.

Also, I've heard of soft contacts before.  You put in substrate contacts but they aren't connected via metal.  They make their contact via the substrate.  Sounds like a bad idea because you encourage the current to flow through the substrate.

It would seem like the 2 basic rules are:
1) put substrate contacts next to devices to provide a non-substrate path for substrate current
2) use wide lines to avoid IR drop, which keeps the voltage difference between substrate contacts to a minimum (thus reducing substrate current flow)

And, I believe that using a capacitor between Vdd and Gnd (bypass cap) to supply charge during large transients will prevent excessive current from being drawn from the supplies at any one time (thus avoiding IR drop on the supply lines).

Thanks!

Marc