Aaron,
I would avoid the resistive attenuator on the output
- use either a pi matching network centred at 2.5GHz with a
loaded Q around 5 and accept the loss of power at 2 and
3 GHz:
50R o---o-----15nH----o----o 1K
| |
0p7 0p33
| |
----- -----
//// ////
or a "T" network if a DC block is required:
50R o----0p3-----o-----0p12----o 1K
|
15nH
|
-----
////
which may become a bit difficult to implement once you accomodate
the MOS parasitic elements. It would be preferable to use a 5:1
transformer (an interesting challenge on chip; but "do-able" and
with an insertion loss of about 1.5dB) which can be implemented off
chip using pcb transmission lines.
You will get a noise figue of about 5-6dB (not 15) and a gain
of about 15dB (not 25.5*) for such a common source amplifier
with a "standard" 0.18um CMOS process.
* I have assumed that your voltage gain is 40x, making the
overall power gain, given a good 50R input match:
20.log((40) - 10.log((1000/50)^0.5)
Actually you should be calculating the MAG (maximum available
gain, or transducer gain Gum) which includes a knowledge of both
the input and output impedances and the matching to them.
Take a look at:
http://www.silicondevices.com/Resources/AppsNotes/SparametersInWinSpice.htmlif you would like to get an idea of how this may be done in simulation.
Cheers,
SimonH.