A_Programmer
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Posts: 13
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I am implementing a compact model for a device using Verilog A under HSPICE. When I check the Verilog-A log file, I find:
"The CML file is up to date. No compilation necessary."
What does it mean? Does it mean that, as long as I don't modify my Verilog A code, no compilation of the model is required even if I change the type of analysis?
Thanks.
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