rajivs1001 wrote on Jul 3rd, 2006, 1:56am:Hello,
I am designing a SC programmable gain amplifier ( PGA with gain 1 or 2 ) using fully differential folded cascode OTA with a SC-CMFB . Load are only capacitive with 25pF at each node. I have some questions in this regard.
1- Is it OK to use OTA for 25pF load cap ?
2- I have 25ns available for settling. How do i divide this time between Slewing and settling ? to be more specific how do I calculate Ibias and UGB.
3- I know how to calculate SR for a normal opamp but not sure how to do it for a SC PGA.
Can someone give me link to any document in this regard or make some suggestions.
Thanks and regards,
-Rajiv
Hi Rajiv,
1. Yes, it is OK to use an OTA, as the load is purely capacitive.
3. The slew rate is calculated in the same way as for an OTA. SR=Iout/Cload. As you are using a folded-cascode circuit with a well-defined load, it should be possible to compute both Iout and Cload just by inspection.
Note that Cload also includes contributions from the sampling cap, feedback cap, and input gate-source cap. You should first compute this effective load, possibly ignoring input gate-source cap for the first iteration. The closed-loop bandwidth will also be reduced when you change the gain from G=1 to G=2, depending on the choice of your SC amp architecture. Slew limiting will kick in harder for G=1.
Now for the harder question on how to divide the 25ns that you have into slewing and settling. Firstly, are you allowed to slew in the application? A lot hangs on this, as the design methodology is different. I assume that you are allowed to slew, since you decided on an SC amp in the first place.
Secondly, how accurate does this gain need to be? Let me make the crude assumption that you are looking at a gain accuracy between 0.1% to 1%, since cap mismatch will anyway limit you to 0.1% at the best. However, if you have other constraints such as THD, then they will decide your gain requirement.
There is no easy method to predict when an amplifier leaves the slewing region to enter linear settling. However, one may assume that this happens when the input to the amp is equal to the (Vgs-Vt) of the input device. You can also write the ideal output as a function of time during the amplification phase as Vo(t) ~ Vfinal(1-exp(-t/tau)), and the slope of this multiplied by the effective Cload will tell you when your amplifier is slewing (Cload*dV/dt > Islew).
For design, I would suggest that you allow about half the clock cycle for slewing assuming that you are looking at 60 dB accuracy from the opamp. Typically, the circuit will have settled to atleast 20-30 dB accuracy by the time you are done slewing. I do an example here assuming 20dB settling at end of slew and 60 dB desired accuracy.
Islew = Cload*dVmax*0.9/(0.5*Tclk) gives you an expression for current needed if you assume only 20 dB settling from slewing.
Ntau = Accuracy(in dB) - 20/ (0.5*Tclk) gives the remaining timeconstants required.
tau = 0.5*Tclk/Ntau (required timeconstant, gm, W/L from Islew information)
By the way, do include margins in your design, and do your tradeoffs. If you can, try the opamp by Castello (JSSC-A micropower switched capacitor filter...).
Regards
Vivek