Hi all,

I need some opinions from all regarding analog functional verification. Nowaday analog circuitry is getting more and more complex and the flexiblity of the circuit increases tremendously with more and more function being integrated in 1 chip. As I go higher and higher in hierarchy, I found it harder and harder to verify the analog block across all PVT and all possible operation mode. For example, if the analog block can work in 4 modes, verifying it using monte carlo for lets say 2 voltage extreme and 2 temperature extreme, even for 20 points per condition will take 320 simulations. I used to design in digital domain where I consider only 2 worst case conditions. How you guys actually verifying large analog blocks with so many mode of operations? My method looks stupid but this is what I can think of to give the highest confidence. Any suggestion?

Thanks,
chase

Hi Ken,

Thanks for the advice. I read the paper but I am still do not have a very clear idea on the subject. In the paper you mention about behaviour modeling of the subcircuits, do you mean that all those subcircuits, at least at the final stage of the design, should model all the worst case behavior? But the worst case output of a circuit is always depends on the worst case input from another circuit. Assume that initially we have ideal models for all circuits, isn't it going to take a lot iterations before getting the "exact" worst case output?

chase

Hello all,

Thanks for the comments. Guess I will have to spend more time doing research the matter.

chase.

You exactly met the automation gap in analog circuit verification!

What you need is

1. Automatic parameter extraction and checking (Aptivia, Matlab extraction, your own code)
2. Simulator/netlist control to set simulation modes, operating modes, corner ... (typical Perl,Phyton, Skill?)
3. Checking the hierachical embedding (is the circuit used or driven as intended)

Everthing must run fully automatic everytime the model, process or the hierachical embedding change.

I expect that in this domain new tools pop up in the future which support existing simulators.

Hi Achim,

focusing on point 1. In ADE you can use a text editor and setup the expression and load it into the Calculator by paste. But for more complex extraction you need a scripting enviroment. I have found a similar tool under www.sourceforge.net MANIAC but I did not test fully. A better way is to have a Phyton library with a Matlab compatible parser and a Waveform tool to test the scripts with real simulation data and derived diagnostic results. But it seems there is no market for that.

I would also add that putting the backprocessing into the simulator like VerilogA or VHDL-AMS stick you mostly to one simulator vendor. If you want to modify the analysis you have to rerun the complete simulation!

jbdavid,

are you working for cadence? If, is there a plan to introduce script based extraction and automatic verification within the next releases? Or new tools?

Hi all,

Seems like being an analog IC designer needs to be a multi-talented programmer as well. I do spend some time on automating monte carlo simulation on some blocks with perl and I find it too time consuming to write a general script good enough to cater all kind of situation and circuit and I end up running the simulation and verification manually.

Heard that cadence are going to have something called neocircuit for design automation.

chase

Achim,

it is natural that you have to follow the more complex nature of today mixed/rf circuits. There is also more programability built into systems. Partly because that is also built in hardware but more because you want to have a higher degree of flexibility to explore alternatives. Executeable languages are a good extension to structural descriptions. I think they complement each other. If your origin is analog and spice you have a good ground which most missing. What is missing is a better support of the EDA world for integrated verification.

Today(!) I am specifying analog/mixed systems on Matlab/Simulink because it is more efficient. For our development Matlab is also used as base for digital as well as analog developments. For me Mathworks is the winner in the analog world. The huge libraries, the scripting enviroment, good documentation,... are the reasons to develop higher level circuit specification. Verification on the next level is still spice but mixed with VHDL-AMS, Verilog.

An integrated verification flow must support automatic or executeable spice level parameters. The methology of the 80's, schematic->netlist->spice->waveform, stick the verification engineer to cockpit drivers. If a circuit runs at 3 temperatures, 3 basic process corners, 100's analog process corners, 10's circuit configuration states, 10's of resuse embeddings, ..., there is no way to proceed with the cockpit procedure. Waveform verification is not automatic!. You can automate up to the point where script based verification could generate weeks of waveform videos. Who verify the videos?

What I think in the near time the solution is to use the same Matlab enviroment for higher level specificaction/design also to drive automatic circuit level verification. That is exact the point where EDA is missing. They need for this was oberserved for about 5 years now. But the was no sign from EDA. All effort is concentrated to some spot issues like simulation result based netlist reduction. This example also shows that if an specification enviroment would exist the extractor does not need to extract aF/mOhm on static or small current lines. So the netlist reduction is good example what going wrong. If the netlist reduction is not ciruit result driven it has the same dilemma.

Ten years ago every one told you the world is digital or going to be. You had to think that you are one of the last dino's waiting for the next asteroid. Now analog productivity is in crisis. For what you need analog? The world is digital. There is something that got wrong.

Reiner