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Jamz_will

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Checking verilog behavioral model
Aug 01^st, 2006, 2:12am

Hi,

Does any one know how can I check the verilog behavioral model if it complies or conforms on the datasheet of a specific circuit. Example for PLL datasheet, how can i validate or check the verilog model if it conforms to what was written on the datasheet. Is this possible?

I have no idea how. Actually this is my assignment from my superior

Please advise.

Thanks

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bernd Senior Member Offline Posts: 229 Munich/Germany	Re: Checking verilog behavioral model Reply #1 - Aug 1^st, 2006, 4:35am http://en.wikipedia.org/wiki/Functional_verification Is that what you try to explain? Bernd
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Jamz_will

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Re: Checking verilog behavioral model
Reply #2 - Aug 2^nd, 2006, 12:07am

Yes thats what im trying to ask. I now have the idea .Thanks.
I only have the datasheet of PLL and the verilog model (behavioral model, functional black box models ). What else do i need? Can you explain it in details how i can validate or check the verilog model if it conforms to what was written on the datasheet.

Jamz_will

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bernd

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Re: Checking verilog behavioral model
Reply #3 - Aug 2^nd, 2006, 1:56am

Common practice is to write a testbench in the HDL the
model is written and supply the model with input stimuli and
examine the outputs signals.

http://www.doulos.com/knowhow/verilog_designers_guide/test_benches/
http://www.amazon.com/gp/product/1402074018/sr=8-3/qid=1154508309/ref=sr_1_3/002...

You self has to know what input stimuli are required for your PLL
and how the output should look like.

Bernd

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Jamz_will New Member Offline Posts: 6 Singapore	Re: Checking verilog behavioral model Reply #4 - Aug 7^th, 2006, 12:34am Thanks. You are a big help. One more question. Is there a tool that can compare cdl/spice netlist to verilog model?
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Andrew Beckett

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Re: Checking verilog behavioral model
Reply #5 - Aug 10^th, 2006, 2:45pm

Yes, a calibrated human being, with the assistance of a simulator! You would simulate the SPICE level design with the same testbench as you'd simulate the model, and see if they behave the same.

If you're after some sort of formal equivalency checker, then none exists for comparing transistor level circuits with analog behavioural models, unlike in the digital world where you have tools for checking the equivalence of RTL versus a gate level implementation.

Regards,

Andrew.

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jbdavid

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Re: Checking verilog behavioral model
Reply #6 - Aug 11^th, 2006, 12:46am

Tools like Aptivia (from Cadence)
are setup to allow you to define a set of measures and run them on both the model and the circuit..
even extract data from the model - insert into the model and then compare that specific measurement points match..
Of course the HUMAN is still strongly in the loop during the setup of the testbench and the defining of the tests.
Jbd

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jbdavid
Mixed Signal Design Verification

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Jamz_will New Member Offline Posts: 6 Singapore	Re: Checking verilog behavioral model Reply #7 - Aug 14^th, 2006, 6:06pm Can I used verilog-a simulator ? I would like to simulate the SPICE level design with the same testbench as I would simulate the model, and see if they behave the same. Is there any free simulator tool for this? Thanks a lot!
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loose-electron

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Re: Checking verilog behavioral model
Reply #8 - Aug 15^th, 2006, 9:44pm

As stated by others, there is no quick and easy way of doing this. It is one of the big reasons a lot of analog behaviorals fall apart. A lot of times people that write code are from a digital perspective and people who design circuits come from an analog perspective.

Behavioral models tend to be done by people who write code and don't have a good grasp of the nuances of analog stuff.

Jerry

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Jerry Twomey
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Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical

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Andrew Beckett

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Re: Checking verilog behavioral model
Reply #9 - Aug 20^th, 2006, 3:35pm

I would say quite a lot of analog designers write Verilog-A models these days (certainly that's what we see in Europe). I've seen very few Verilog-A models written by digital designers - having Verilog language skills is less of an advantage than having analog circuit understanding when it comes to writing a behavioural model.

Andrew.

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loose-electron

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Re: Checking verilog behavioral model
Reply #10 - Sep 21^st, 2006, 12:47pm

Andrew:

No argument, for SOC things you need to go there.

There's a lot of analog folks who have resisted doing so. However, it is happening.

Call it the "grumpy old man" or "Bob Pease syndrome"
("Bah Humbug!!! All simulation stuff is junk and Spice is a total piece of trash..." )

Bob's gonna kill me! ;D

Jerry

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Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical

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