Designer’s Guide Community

lrc

Junior Member

Offline

Grrr....

Posts: 11
U.S.A

a basic verilogA question
Sep 29^th, 2006, 7:01pm

Hi,

I am trying to model the following actions. At the rising clock edge, A is assigned a value. After tdelay, B is assigned.
How should I create the delay in assignment in verilogA? Is the following approach reasonable?

@(cross(V(clkSig)-vtran, +1, slack, clkSig.potential.abstol)) begin
A = xxx.
currenttime = $abstime
@(timer(currenttime + tdelay))
B = xxx.

I am a beginner verilogA. I will appreciate your help.

thanks,

LRC

Back to top

IP Logged

Ken Kundert

Global Moderator

Offline

Posts: 2384
Silicon Valley

Re: a basic verilogA question
Reply #1 - Sep 29^th, 2006, 10:15pm

You can not place an event statement within an event statement. Conceptually this does not make sense. An event is something that occurs at an instance and has zero duration. Thus the second event statement could never get called. Verilog-A is different than Verilog in this regard. In Verilog, an @event statement would cause execution of the thread to block or hold at that point until the event occurs. In Verilog-A statements do not block. The statements are evaluated for all time, and each statement has zero duration. So in Verilog-A, an @event statement is simply bypassed except at the instant when the event occurs.

To implement what you want, try something like the following
Code:

@(cross(V(clk)-thresh,+1)) begin
    A = ...
    next = $abstime + tdelay;
end
@(timer(next))
    B = ...

-Ken

Back to top

IP Logged

jbdavid

Community Fellow

Offline

Posts: 378
Silicon Valley

Re: a basic verilogA question
Reply #2 - Sep 30^th, 2006, 2:20am

probably some of the confusion for digital guys is that in the Discrete time domain we have the possibility of
BLOCKING events and delays at the beginning of the line..
Code:

always @(A) begin
  #4 B = !A;
  #4 C = !B;
end

which has NO equivalent in the analog side
instead you should think about your model as if you could only use something like:
Code:

always @(A)
 B <= #4 !A;
always @(B)
  C <= #4 !B;

kens example is like this..
jbd

Back to top

jbdavid
Mixed Signal Design Verification

IP Logged

lrc Junior Member Offline Grrr.... Posts: 11 U.S.A	Re: a basic verilogA question Reply #3 - Oct 2^nd, 2006, 7:03am Thanks very much for Ken and jbDavid's help. I understand better now.
Back to top	IP Logged