You could simply code a veriloga diode, C, R envelope detector. If i remember correctly, i think one of the first examples on the Cadence veriloga training course.
For modelling the startup behaviour of a vco you could you not just multiply the output signal by an envelope function desribing the envelop growth?
don't forget the resourses available on this web domain... look at the veriloga examples
http://www.designers-guide.org/VerilogAMS/index.htmlcheers
aw