ccc
New Member
Offline
Posts: 3
MTK Lab@NTUEE, Taipei, Taiwan
|
Hi, I am interested in your phase noise simulation for frequency divider. I am currently designing injection-locking frequency divider. Did you simulate your divider by SpectreRF? I not know how to set the enviroment. In my divider, I have a input (Vsine) port which is operated at 30GHz. I design /2, and the divider output frequency is 15GHz. I found that appears errors at PSS simulation. Could you tell me more detailly how you simulate it? Thank you for your help.
Best regards, CCC
|