Hi,

I've used verilog-A models for VCOs before.  Typically they provide a sinusoidal output.  I model the phase noise by providing thermal noise at the vco tuning port.  A resistor sized appropriately for the desired noise @ a particular offset can accomplish this.  I simulate using PSS and PNOISE, and get the desired phase noise profile at the vco output.

But when I use the verilog-A VCO model proposed in "Modeling Jitter in PLL-based Frequency Synthesizers", the same trick doesn't seem to work for me and I'm wondering if someone can offer an explanation as to why?  The output of this model is a square wave as opposed to the sine wave model I'm accustomed to using, but shouldn't the effect of the noise at the VCO input on the square wave zero-crossing be captured in a PSS/PNOISE solution?

Thanks,
Jeff