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internal timestep too small (Read 14701 times)
xwcwc1234
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internal timestep too small
Aug 11th, 2006, 3:17am
 
Hi ,
  I use Hspice's transient analysis to simulate a PWM circuit with LC low pass filter at output . Buy it always has "internal timestep too small" problem after all. I try to fix this problem by changing RMIN & TSTEP value , but it can not work . Anyone knows how to solve this problem ?
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Geoffrey_Coram
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Re: internal timestep too small
Reply #1 - Aug 14th, 2006, 4:56am
 
Internal timestep too small is usually an indication of a derivative problem.  What transistor models do you have in the circuit?  Do you have any behavioral models or strange dependent sources?
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xwcwc1234
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Re: internal timestep too small
Reply #2 - Aug 14th, 2006, 7:45pm
 
I use BSIM3V3 model form foundry and there is no behavioral model in my circuit . In my circuit , since it is a PWM circuit , so there are a couple of big NMOS/PMOS transistors at output side . I also put a LC low pass filter (L=33uH ,C=1uF) to filter out the PWM output  . Hspice diagnostic for nonconvergent are show as follows ;



                       node    subcircuit       old       new      error
                       name    definition    voltage   voltage   tolerance
                      (xt.sp)     t89           -7.996k    -6.996k  125.065
             (xt.xi228.pdrive) out_blk     5.363      5.343     3.748
                  (xt.r101:i1)  t89           -7.996k    -6.996k  125.065

    total voltage source power dissipation=  -18.5695        watts

          So what can I do for solving this problem ?
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Re: internal timestep too small
Reply #3 - Aug 15th, 2006, 5:00am
 
Is the PWM output fed back to the circuit, like for an LDO regulator?  Can you break the feedback loop?  Try feeding the control with a voltage source instead, and see if you get a reasonable output.  8kV is awfully high.
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Re: internal timestep too small
Reply #4 - Aug 15th, 2006, 9:50pm
 
Added Item:

The inductor sounds like it is ideal.  Reduce the Q of that perfect inductor with some series resistance and parallel capacitance. Ideal reactive elements can do some strange things in simulators.

Jerry
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Re: internal timestep too small
Reply #5 - Aug 16th, 2006, 2:15am
 
(1) I modify the inductor model with serise resistor and parallel capacitor , the result is the same.
(2) The PWM output is feedback to a integrator  , why I have to break the feedback loop to fis this problem ? Is the feedback loop cause this problem ?
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Re: internal timestep too small
Reply #6 - Aug 16th, 2006, 6:20am
 
I was suggesting you break the feedback loop just for diagnostic purposes, to make sure the system works correctly open-loop.
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Re: internal timestep too small
Reply #7 - Aug 16th, 2006, 11:33pm
 
I added the Hspice options itl4=100 & reltol=0.01 in the spice file , and the result looks better . I also try the method=gear to fix this problem , but the simulation waveform has a little bit strangle. Is the Gear method not accurate as  Trap ?
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Re: internal timestep too small
Reply #8 - Aug 21st, 2006, 10:24am
 
reltol = 0.01 is huge -- that means you're allowing the simulator to "lose track" of 1% of the largest current going into any/every node.

itl4=100 is also not always such a good idea.  You're telling the simulator to try 100 iterations before giving up and choosing a smaller timestep.  The default is 10, and most transient analyses average less than 5.  You could be making your simulation run a lot slower than it should.  It would be better to get to the bottom of the convergence problem.

Gear is more numerically stable than trap.  Ken's book (DG to Spice&Spectre) is one place to read up on the integration methods.  Or "google" the terms.
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Re: internal timestep too small
Reply #9 - Aug 21st, 2006, 6:15pm
 
I use Hspie option ITL4=100 and TRTOL=25 and then it work . The error message disappear and the simulation run smoothly. Why ?
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Re: internal timestep too small
Reply #10 - Aug 22nd, 2006, 3:51am
 
Luck?
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