The most common corners are Process, Voltage and Temperature (PVT)

A couple things:

Temperature needs to be run from cold (lowest environement temp) to hot (highest environement temperature PLUS the internal self heating of the chip as per wattage and thermal package model)

Voltage - I always suggest that people design initially using a voltage slightly less (say 5%) than the minimum power supply voltage. I can not counbt the number of times I have seen a designer do design at nominal power and then have the circuits turning off (or messed up bias in one form or another) when they test the low voltage corner.

Process - These corners are a bit of a nuisnace - the "TT" "SS" "FF" etc (probably TSMC models?) need to also be run in the "SF" and "FS" corners as well. When the PMONS/NMOS mismatch, sometimes you run into issues as well. Also, you have resistors, capacitors, etc in the process that lead to additional corners requiring a look see.

Consequently you can get into a lot of corners that need to be run.

For whateve it is worth I tend to design in the:

-- lowest voltage power
-- lowest bias current (often high resistance corner for that)
-- SS models,
-- hottest temeprature

Not saying that that is always the worst place to be, but it is the noisest, and slowest for a lot of designs. Also, make sure you cover matching issues and parasitics as well.

I am biased here, but have you had any trianing in there areas? I bring a training course on-site for designers, that is pretty useful:

http://www.effectiveelectrons.com/training.html

Yes, I'm biased, but I have gotten a lot of good feedback on the courses.
The one day "show stoppers" course is valuable for any and all designers (at all expereince levels), and the three day course in practical aspects of design is good for people under 5-8 years in analog design.

My favorite comment at the end of the courses are invariably the ones "if we had known <blah> before we taped that last chip out..."
Well, I am trying to minimize design respins is why I am providing the training programs.  ::)

What I tell the managers - It costs you somewhere between $100,000 and $1.2 million dollars to fabricate a chip, right? And three months of design engineer time? This is a comprehensive training program for your entire design team, with the motivation being to eliminate the "big problem issues" in designs. Considering how little it costs to do, only the "Pointy Haired Boss" in Dilbert would see it as a waster of money.

If you have any other questions on corner, post them and I shall try to answer them.

hope that helps,
Jerry

Happy to be of help, good luck with it!