Hey all -  A new topic.

This one is about what problems you have had.  It is kind of a global question, because I am looking for additional topics to supplement a training course I do in this area. I already have a huge number of case studies -  "you need to look out for this" stuff, but am always looking to add material.

In my experience, the big problems with mixed signal chips reduce down to two major areas:

-- Intereference noise due to analog-digital compatibility issues.
-- Simulations that do not do the same thing as the silicon, due to a poorly defined model.

So what problems have you had in your designs? A brief description of what the problem is/was and what you determined to be the issue would be much appreciated.

Jerry

Andrew:

A good post. I totally agree withy you with respect to the paranoia statement.
In my opinion, being a bit obsessisve-compulsive about all the fine details are what gets things to work the first time.

I do see a lot of problems with mixed signal noise issues, and a number of problems with models, if people take the models and don't question them.  Especially certain foudries produce inferior models and design kits.

Also, if you are going out on a foudry with good models, your success rate is much improved. However, size of foundry and quality of models and PDK generally have nothing to do with each other.

A lot of the noise problems occur when digital designers own the top end of the chip.

My other favorite is when people decide to plug an RF front end into a mixed signal chip. Never say never, but I know of only 2 examples where people have gotten this working without problematic noise into the LNA.

My take on that - get the design done with a dedicated LNA mixer chip first, and then if they insist on trying it, do it as a secondary path.

Thanks for the feedback, I was begining to think that everyone had 100% perfect first time functional ships here.

Jerry

A good related question is "What ALMOST killed your chip.?"
IE.. something NOT caught by a tool..

my  list is fairly short..
Wrong order of bits between analog and digital interface out of ADC..
customer only needed 4 of 6 bits.. and almost got the low 4 bits.. Verilog-A Models simulated with digital was the only thing that caught this..
Not running simulations from the final schematic database.. Designer added a bit to a DAC, simulated it and fixed the layout, but forgot to
copy the final schematic to the "real" database.. and was not around when the final LVS error showed up.. so we "fixed" the lvs error and his
DAC has worse performance than before.. (since the two low bits are tied together!)
Thus I discourage the practice of COPYING the design out to a development area, and encourage use of Design Management software..
and RE-running simulation AFTER check in..

Noise, electromigration..

Hope this helps..
jbd

You just gotta remember though, EVERYONE knows the right way to get the design done right.  ..
And they don't need to buy any more tools.. or hire any consultants..
until the chip comes back and doesn't work..

jbd

# 1a  Poor communication - Customer either has no real idea of how he wants to use the chip, or does not know which parameters are really critical and so leaves some unspecified, until he uses the chip in the app and then realizes
#1b Poor system design - The above can also be counted as poor system design.

In the end, the customer refuses to take the chip, and so effectively, the chip is dead even if it meets all your specs as specified.

#2 Poor understanding of parameters: For instance, what exactly is meant by DC gain and how much do you need, and why? I have often heard people discuss how they need >120 dB DC gain, but only 70 dB settling accuracy will do. DC Gain means nothing, it is the accuracy to which the opamp inputs settle that counts. People learn this the hard way by measuring their chip results, and/or when they begin designing gain-boosted opamps and run head on into doublet-related settling issues

#3 Muxing testmode pins onto analog pins without giving a thought to what might happen there in normal mode

#4 Forgetting about the voltage range that a switched-cap circuit can handle. People forget about this, and get "mysterious" errors from charge-pumping action."

#5 Poor layout: Despite the well-known fact that fully differential circuits are not fully differential unless you have made a perfectly matched layout, people go on laying things in strange and sometimes downright unacceptable configurations, and then see even-order distortion, noise problems etc.

A lot of the problems can be classified as system-level issues. The list of such things could go on endlessly of course.

Regards
Vivek

First time I killed a chip, wrong connection at the top level. I had not simulated the whole chip because it needed too much time. I found the error when the chip was shipped back. Corrected with metal change.

Second time I killed a chip, wrong change at the last minute. I changed the polarity of power down for one block at the last minute before tape out. I was so tired that I made a wrong dicision. I found the error before the chip was shipped back, and corrected using FIB.


Best regards,
Yawei