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How to creat a VCO model with jitter in VerilogA (Read 1491 times)

semitao Junior Member Offline Posts: 20	How to creat a VCO model with jitter in VerilogA Aug 15^th, 2006, 6:19am Hello! I just read the Modeling Jitter in PLL-based Frequency Synthesizers by Ken Kundert. In this paper, there is a VCO model that includes accumulating jitter. But this model generates square waves, I want a VCO model generates sine waves. How can I modify this model to generate sine waves? Best regards!
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Ken Kundert Global Moderator Offline Posts: 2384 Silicon Valley	Re: How to creat a VCO model with jitter in Verilo Reply #1 - Aug 15^th, 2006, 8:32am In the VCO model given in the paper replace the last line of the model, Code: V(out) <+ transition(n ? Vhi : Vlo, 0, tt); with one that computes a sine wave based on the phase variable already present in the model. Code: V(out) <+ ampl*cos(phase); -Ken
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semitao Junior Member Offline Posts: 20	Re: How to creat a VCO model with jitter in Verilo Reply #2 - Aug 15^th, 2006, 5:44pm Thanks, Ken. I have tried this statement. When I used a 1V voltage as the input signal, the output of VCO is very strange. I don't know the reason. Best regards!
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Ken Kundert Global Moderator Offline Posts: 2384 Silicon Valley	Re: How to creat a VCO model with jitter in Verilo Reply #3 - Aug 15^th, 2006, 6:19pm try putting a boundstep() function to assure that the simulator takes a reasonable time step. The boundstep should be no more than 0.1T. -Ken
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semitao Junior Member Offline Posts: 20	Re: How to creat a VCO model with jitter in Verilo Reply #4 - Aug 15^th, 2006, 7:01pm Thanks, Ken. I have tried your method, and VCO works. Thank you! Best regards!
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semitao Junior Member Offline Posts: 20	Re: How to creat a VCO model with jitter in Verilo Reply #5 - Aug 15^th, 2006, 7:07pm By the way, why the model doesn't need the bound_step statement, when the VCO outputs the square waves. Best regards!
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Ken Kundert Global Moderator Offline Posts: 2384 Silicon Valley	Re: How to creat a VCO model with jitter in Verilo Reply #6 - Aug 16^th, 2006, 12:02am The transition statement forces time points at the corners of the waveform.
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semitao Junior Member Offline Posts: 20	Re: How to creat a VCO model with jitter in Verilo Reply #7 - Aug 16^th, 2006, 12:34am Thank you!
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