grosser wrote on Aug 18^th, 2006, 10:23am:


It is suitable for feedback generally. It is essentially an improved version of Middlebrook's method. It uses exactly the same simulation setup as Middlebrook's method with just a different formula for calculating the loop gain. The result is independent of the orientation and the position of the probe in the loop (provided there is only one feedback loop in the circuit, see the article mentioned by Ken in reply #4 for details).

I would like to add two remarks here:

What is generally known as Middlebrook's method for measuring loop gain is not the method described in his GFT manual but the method presented in his much earlier article "Measurement of Loop Gain in Feedback Systems", Intl. J. of Electronics, 38, 485—512, Apr. 1975. This method neglects backward transmission.

The definition for loop gain given by Middlebrook in his GFT manual is slightly different from the definition given in the article mentioned by Ken (http://www.thekunderts.net/ken/docs/c%26d2001-01.pdf) which is used for Spectre's stb analysis. In terms of equation (20) of this article, the expression for Middlebrook's definition of loop gain would be T=k₁/(k₃+Y_e+Y_f). The advantage of Middlebrook's definition is that it is more closely related to the closed-loop gain of the circuit. Its disadvantage is that it is not symmetrical, the orientation of the probe does matter in his case. In most practical cases, the difference between both definitions will be negligible (if the probe is oriented correctly for Middlebrook's definition). Both definitions of loop gain will always tell you correctly if a circuit is stable or not, and there will generally be only very minor differences in calculated phase margin and gain margin.

To me, it looks like there are two feedback paths in your circuit: one via R1, where you put your probe, and another one via the opamp at the left of the schematic, which you are currently missing. You need to put the probe in a place where both loops are joined together. This would be either the + input of the opamp in the middle of the schematic, the output of this opamp (which is also the gate of the output PMOS), or the drain of the output PMOS. Ideally, you should get the same result in all three cases.

I did a test to check what results Middlebrook's method gives compared to large LC method.

I don't know what results are reliable. If i put probe circuits in the places marked by red arrows the results are completely bad.
The simulation results(linked) come from attached test bench.

http://img211.imageshack.us/my.php?image=acopenip3.png

yellow curve is a Middlebrook's method result and the red is from LC method.

I don't understand why yellow gain increases in high frequencies and i wonder if i can rely on these results

regards

Do you know how to plot the phase of this formula ((I(V3)/I(V4))*(-V(x)/V(y))-1)/((I(V3)/I(V4))+(-V(x)/V(y))+2) in Hspice?

Sorry, I'm not familiar with HSPICE either. However, I have added the formula for the symmetrical loop gain of Spectre's stb analysis for your configuration, where the circuit is duplicated, to my example at http://groups.yahoo.com/group/LTspice/files/%20Examples/Educational/LoopGain_Pro.... If you use this formula instead of Middlebrook's, you will not have to pay attention to the orientation of the probe.

grosser wrote on Aug 22^nd, 2006, 10:44am:


Hi, grosser

I was wondering how you do the simulation by applying Middlebrook's method.  Can you give me more information or details ? Thanks you in advance.

Actually, I applied a method like LC method. Two resistors are added like the way in LC
method. RR1 node1 node2 "value of DC resistance" "value of AC resistance".
            RR2 node3 node4 "value of DC resistance" "value of AC resistance
The value of DC resistacnce of RR1 is set to small and value of AC resistance of RR1 is set to very high. RR2 does the opposite of RR1.

Thanks for the information. I used stb analysis from spectre to run for the loopgain of my LDO. Attached is the block diagram of the circuit. I tried to break the loop at 3 locations, 1 is at the input of the 2nd stage op-amp, 2nd is at the input of the pass element (big PMOS), and 3rd point is at the input the of first stage op amp. I suppose wherever i break the loop as long as it is within the feedback loop, then i would get the same result. I get exactly the same loopgain and phase margin if i break at the 2nd and 3rd break point. But i would get different value of DC loop gain and phase margin if i break at the 1st point.  :o  :-/ Can anyone advise me why is the case?
Thanks in advance