in Cadence you can use a profiler to see where the simulator is spending its time..
Generally speaking simulator time is
Behavioral < RTL < Gate,
but ALL of those are much faster than solving the analog circuit..

to get the most speed out of Verilog-AMS I look for places where the analog data is SAMPLED, or can be treated like a sampled system..
for those I use WREAL rather than electrical.. as this moves the signal out of the analog solver.
(my Tutorial from BMAS  4 years ago talks about this method a little and my paper from two years ago started the ideas in my head for
using logical signals on a differential signal pair.. which I expand on in this years paper.. (there is still time to register.. assuming your in the USA.. or can easily travel here..)

Its the Analog simulation that generally consumes the most resources so thats where you need to focus your modeling effort.
Jonathan