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duty cycle requirement for the input of CDR (Read 4973 times)

dandelion Community Member Offline Posts: 98	duty cycle requirement for the input of CDR Aug 24^th, 2006, 12:16am Hi, In normal conditions, what is the requirements of the duty cycles or PWD(pulse width distortion) for the input of the CDR?The input is TTL/CMOS level. Thanks fo the help.
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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: duty cycle requirement for the input of CDR Reply #1 - Aug 24^th, 2006, 10:14am John: CDR? Could you please define? tnx, Jerry
Back to top	Jerry Twomey www.effectiveelectrons.com Read My Electronic Design Column Here Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical IP Logged

Ken Kundert Global Moderator Offline Posts: 2384 Silicon Valley	Re: duty cycle requirement for the input of CDR Reply #2 - Aug 24^th, 2006, 1:17pm CDR = Clock and Data Recovery. A key block in the receiver of a SerDes. -Ken
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email_gz Junior Member Offline Posts: 31 gaoz.mail@gmail.com	Re: duty cycle requirement for the input of CDR Reply #3 - Sep 5^th, 2006, 8:59pm If you use only one of positive or negtive edge to Tx/RX , duty cycle ,I think , is not a big problem. But If you use both positive and negtive edge to Tx/RX ,you should have a 50% duty cycle synchronous clock.
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ywguo

Community Fellow

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Posts: 943
Shanghai, PRC

Re: duty cycle requirement for the input of CDR
Reply #4 - Sep 5^th, 2006, 11:38pm

John,

For a CDR, duty cycle distortion(DCD) or PWD is a part of the deterministic jitter. It reduces the sampling window, which means a smaller eye.

The total jitter, deterministic jitter + ramdom jitter should be less than the a cycle. Normally we do not have a special requirement on DCD only.

Best regards,
Yawei

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