Hi,

Just a couple of points:

1. As far as I know, it is CDS that causes a greater increase in noise power and not chopper stabilization. The noise power for conventional CDS goes up by 2x at higher frequencies => Double the thermal noise power.

2. CDS is typically easier to apply in switched-capacitor amplifiers. The big question is whether you are allowed to present a switched-capacitor load at the input of your amplifier or not. If not, then chopper stabilization is probably the only solution.

3. In general, if you use any modified form of CDS, then you can always compute its noise gain by writing out the discrete-time transfer function seen by an input-referred noise source. For example, classic CDS (see Gregorian & Temes) gives an NTF H(z) = (1-1/z), which is equivalent to h[n] = [1 -1]. The power gain of this by Parseval's theorem is simply sum(|h[n]|^2) = 2, which is the noise gain for thermal noise at high-f, and around DC, the gain = 0 which is how it remoes offset and 1/f.
You can use this to any DT scheme.

4. If you present a sampling front-end, then you end up with a DT system, and your net noise is proportional to the various capacitances that you use. Typically, it is advisable to use a purely CT solution if power is of concern. I would advise chopping.

The power spec is tight, but you have not specified the noise you want. It looks feasible nonetheless.

Regards
Vivek

ytass wrote on Aug 31^st, 2006, 4:51pm:


Hi,

For more details, see pg. 500-513 of the text by Gregorian and Temes (Analog MOS ICs for Signal Processing), and/or Section 2.2 in http://www.designers-guide.org/Analysis/sc-filters.pdf
These deal with the issue of noise in sampled systems.

More specifically:

2. If you have a switched-capacitor circuit, then the input branch is a capacitor which is connected to the input (vin) each cycle. This charging and discharging is not always tolerable in every system. Firstly, if the biological signal source in your system does not have sufficient drive capability, then you will be loading it severely. A switched-capacitor circuit is essentially a time-varying low-impedance load. Mostly, you would place a high-impedance network at the input, like the gate of a CMOS transistor, so that the signal source sees no load and needs to provide no current.

With standard CDS (offset sampling at input), this is not possible. However, with chopper stabilization, you can chop at another point in the system such as the output. You can of course use a modified form of CDS where you sample the offset at the output of your preamp and then cancel it (see the excellent textbook by Razavi where he discusses this in Section 13.2). The requirement is that the gain of the stage be small enough that you do not saturate it while measuring the offset, but this should be possible if you use a multi-stage preamp and perform offset cancellation on each stage.

4. Regarding noise, please read the above references. Essentially, the thermal noise power taken in a sample (sampled system) is constant = kT. When you normalize this to a voltage stored on your cap, the voltage noise level is kT/C, where C is the sampling cap. The noise contributed to an output sample by an amplifier in a sampled system is also proportional to kT/Cc, where Cc is the compensation cap, and the proportionality constant is dependent on the amplifier configuration and design. Thus, in a sampled system, reducing noise => increasing C => increasing power.

Thus, wideband noise from all frequencies is aliased down in each sample.

If you have a purely continuous-time system on the other hand, only the noise contained within the bandwidth of your system comes into play.

However, since you are anyway taking samples of the input and averaging them, you have a sampled-data system at some point. The key is to design the system in such a way that the net noise required is achieved without too much power consumption.

I hope this helps. But the topic you are interested in is quite a comprehensive one.

Regards
Vivek

For the low power consumption cited why get so fancy with chopper stabilization and similar?

Most offsets are pretty static and can be taken care of with a DAC summation in to compensate for them. That can go thru periodic updates in the background.

Also, since this is low frequency I expect that there is an ADC and DSP downstream? If so, the ADC output can be used to tweak the offset thru digital feedback  to the offset DAC. Little or no power consumed. (at low frequencies anyhow)

Also, within limits of ADC range, offsets can be removed digitally from the quantized signal content as well.

Other options include analog feedback with low bandwidth, considering you are going around 50-80dB of gain. THat will cause a high pass effect in the forward signal path, so you need to select your BW (near DC) in order to not encroach on your signal of interest.

Investigate some of the offset comepnsation techniques used in the analog baseband gain/filter architectures for GSM receivers. It is a similar problem.

Jerry

Hi Jerry,

I think the main issue here is 1/f noise and not offset, since biological signals are typically if the low-f range where this noise is very high. A simple offset calibration will not really remove it. In any event, it is not stated if there really is an ADC down the chain.

Autozeroing through CDS or chopper stabilization is not that hard and is more robust. Some autozeroing schemes do use the auxiliary slow feedback path that you mention.

Regards
Vivek

loose-electron wrote on Sep 7^th, 2006, 11:08pm:

Quote:


Agree, but it is necessary if 1/f noise has to be removed.

Quote:


The system can be made with ac coupling, and each stage can sample its offset at its output. This is a common way of doing things.

Quote:


Averaging does not require that an ADC be used, analog averaging can be used, and I think that is the case here.

Regards
Vivek

Ytass:

For clarification - there are a handful of questions I think we could use some answers to:

Is the system analog end to end or is it analog followed by an ADC-DSP system?

Is the preference sampled in time (clocks, SC, chopper etc being viable) or continuous in time?

Is the system cost/size limited? (some of the analog averaging and switched capacitor structures take up space and drive cost up, largely due to the capacitors needed.)

What is your foundry process? (I see 3.3V power stated, but is this CMOS, BiCMOS or what? Also, if you are doing switch-cap designs, then some foundry model sets don't have proper capacitiance distribution in the models, and the charge injection simulations are messed up.)

Is this a battery powered application under a Li-Ion (Or Li-something) battery? (If so, the nominal power of 3.3 might want to be set to a minimum of 2.8 and a nominal of 3.3V)

Those are the questions that come to mind. Am I forgetting anything?