Visjnoe
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Hello,
I'm just interested how most of you do a area/power estimate of analog IP (prior to development, during prestudy), besides these approaches:
1. Deduce based on in-house IP 2. Deduce based on publications (papers)
In general, I believe it would be nice if there were more papers presenting power estimators for certain building blocks (e.g. pipelined ADC), which correlate well with simulated/silicon results. There are a few, but a lot of building blocks are lacking.
Power/area is often the thing that potential customers are most interested in...
Kind Regards
Peter
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