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grosser

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ldo undershoot
Sep 02^nd, 2006, 11:25am

hello

i want you to have a look at the picture.

It presenst's LDO's output for two different output capacitor values 1uF(yellow) 0.15uF (red).

My question is. Does this undershoot depend only on the phase margin?

I think not only on this, but also on the opamp's slew rate current.

I don't understand it, for Cout=1uF case opamp's output current is slower than for Cout=0.15uF case.

If i use additional compensation and improve phase margin for Cout=0.15uF case, the undershoot is still larger than for 1uF and opamps requires much more current to lower it.

Can you tell me why it is so?

regards

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ldo_out.PNG

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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: ldo undershoot Reply #1 - Sep 3^rd, 2006, 1:46pm Remember - when a device goes non-linear the "linear feedback system" is only part of the issue. Cicuits slammed high or low have recovery times, and things of that nature. Take a look at each and every stage of your circuit and observe how each one of them responds.
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mosman Junior Member Offline Posts: 22 china	Re: ldo undershoot Reply #2 - Sep 3^rd, 2006, 6:23pm i agree with loose. PM is the linear specs. but when circuit is in non-linear region the PM can not tell everything. additionally, i observe in your result that the output is very small (about 0.8v). what is the supply? and the step is very small! from this it seems thant your circuit is under non-linear state.
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grosser

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Re: ldo undershoot
Reply #3 - Sep 4^th, 2006, 12:44am

mosman wrote on Sep 3^rd, 2006, 6:23pm:

i agree with loose. PM is the linear specs. but when circuit is in non-linear region the PM can not tell everything. additionally, i observe in your result that the output is very small (about 0.8v). what is the supply? and the step is very small! from this it seems thant your circuit is under non-linear state.

what does it mean the circuit is in the non-linear region? and why this is happening only for 0.15uF not 1uF.
If PM can't tell me everything what else can do that? Is the only way to increase the opamp's output current?

Right, Vout is small, the supply is 1.3V

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sck236

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Re: ldo undershoot
Reply #4 - Sep 4^th, 2006, 5:34am

Try to measure the output resistance including the output capacitor vs. frequency.

This might give you an answer.

Switching load contains the components of high frequency where the the feedback of the error amp does not work.

Then, the output resistance of the LDO could be large for the high frequency since the feedback does not work.

If the output resistance is large, it is obvious that the undershoot is large.

To minimize the output resistance for high frequency, the capacitor should be added at the output of the LDO since the impedance of a capacitor is getting smaller for higher frequency.

Larger capacitor guarantees the smaller output resistance over the wide range of the frequency.

To minimize the output capacitor, maximize the bandwidth.

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caosl_zju

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Re: ldo undershoot
Reply #5 - Sep 4^th, 2006, 5:36am

hi,grosser
First,the ac analysis is linear analysis,it cannot tell you fully about large signal response information,for example,load regulation in ldo.Generally,the pm is used to indicate the stability,but in some time,you cannot get the perfect stability performance even at good pm.The reason is large signal input has changed the quiescent operation point,the pm you get is good only at a point,not at all.
Second, i guess the figure you attached is a load regulation response of ldo.Yes,indeed,under the larger output capacitor,the undershoot will be less.Remember that when a large step load current was added at output,the ldo can not regulate instantaneously to debase the voltage at gate of PowerMOS.assure pmos you use.At this time,who supply this large load current?Only output capacitor.The larger capacitor,the larger amount of charges.The current flows through the capacitor's equivalent series resitance(every capacitor has this resistance),the undershoot voltage give birth.
So, you enlarge the pm will not change this undershoot voltage,just enfluence the stability and settling time.

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grosser

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Re: ldo undershoot
Reply #6 - Sep 4^th, 2006, 6:33am

Many thanks to everyone, i am extremely satisfied.

to sck236

you wrote:

"Then, the output resistance of the LDO could be large for the high frequency since the feedback does not work.

If the output resistance is large, it is obvious that the undershoot is large.

To minimize the output resistance for high frequency, the capacitor should be added at the output of the LDO since the impedance of a capacitor is getting smaller for higher frequency."

by "the capacitor" you mean the standard output capacitor or additional integrated one?

regards

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sck236 Junior Member Offline Posts: 15	Re: ldo undershoot Reply #7 - Sep 4^th, 2006, 5:01pm standard one
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ycj

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Posts: 4
Hsin Chu, Taiwan

Re: ldo undershoot
Reply #8 - Sep 4^th, 2006, 7:05pm

grosser wrote on Sep 2^nd, 2006, 11:25am:

hello

i want you to have a look at the picture.

It presenst's LDO's output for two different output capacitor values 1uF(yellow) 0.15uF (red).

My question is. Does this undershoot depend only on the phase margin?

I think not only on this, but also on the opamp's slew rate current.

I don't understand it, for Cout=1uF case opamp's output current is slower than for Cout=0.15uF case.

If i use additional compensation and improve phase margin for Cout=0.15uF case, the undershoot is still larger than for 1uF and opamps requires much more current to lower it.

Can you tell me why it is so?

regards

True, increase phase margin won't do any good to the undershoot, in fact, it even make the situation worse.

Increase the slew rate may help, since it looses the physical limitation and let the err amp act more linear. A better solution is to increase the loop bandwidth ( + increase the slew rate ).

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