jbdavid
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if you are Running this in spectre - you might want to actually use the spectre language the way you say you do.. or switch it to lang=spice
.. one reason I don't like spice language is that you cant connect by name and originally you could name your nets.. some people still number them which is quite confusing..
I've been reading NAMED net netlists for so long I don't even remember the order of bjt transistor pins.. verilog style module ringosc (output electrical out1, inout electrical Gnd, Vcc);
ttl7404 inv1 (.in(out5), .out(out1), .gnd(Gnd), .Vcc(Vcc); ttl7404 inv2 (.in(out1), .out(out2), .gnd(Gnd), .Vcc(Vcc); ttl7404 inv3 (.in(out2), .out(out3), .gnd(Gnd), .Vcc(Vcc); ttl7404 inv4 (.in(out3), .out(out4), .gnd(Gnd), .Vcc(Vcc); ttl7404 inv5 (.in(out4), .out(out5), .gnd(Gnd), .Vcc(Vcc);
endmodule Ah.. .. hm. in calculating the dc op - if out1 - 0 then out5= 0 and out1 = Vcc.. the only viable op point is all outputs at Vswitch if, as jerry says, you force any one node to 0v the gate driving that node will sink a lot of current, but thats the one that will switch forst after the transient starts...
good luck
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