Hi,

Could somebody suggest(/point to links) the key differences between the LVDS line driver and CML driver design in terms of biasing conditions for the input differential Transistors pairs.

the biassing seems simple to me..
once you've determined what gain you need, thus what your Itail is, you just need to be sure that
Vcm_in + Vswing_margin  < Vcm_driver

on SOAPBOX

that EEtimes article complains that CML is not standardized enough..
I would actually say the LVDS, PECL, ECL and a number of the other Standardized Chip-to-chip interfaces  are subsets of CML-class gate output stages..

the term Current Mode Logic applies to ANY gate that implements a logical function by selectively steering current to (or from) one of a pair of nodes..

The MAXIM article claims that a 50Ω load is "standard" but in fact
even this is selected by the gate designer based on speed, output swing, common-mode level and power requirements
Also both of these articles show only bipolar implementations..

Why common mode level? - many gates have 2, some have 3 (and in some echnologies even 4 ) inputs - each of which might have a different common mode level..
(IE in a 100mv swing logic family you might have Vdd - 50mv as the BASIC output (A-level)
then Vdd - 150mv as the B (for the second input) Vdd - 250mv for the C and Vdd- 350mv for the D level..

of course if you had a 300mv swing it'd be -150 -450 -750 and -1050mv
which even with a low Vt device of 250mv - the lowest pair, driven by a single transistor current mirror  would need Vdssat +vth to be below the commonmode level.. If one assumed only 100mv overdrive to put the transistor in saturation
you'ld need Vdd-1050mv > 350mv+250mv => Vddmin = 1.65v which'ed be prettty hard to do in 90nm cmos.. with a vdd max below 1.0v..

Now if someone tries to tell me to use a "Standard CML interface" I'll ask "Which Standard?"
(Note that XAUI, XFI, FBD, ECL, PECL, SATA, PCI-X are just a FEW of the Standardized interfaces that use CML buffers for their output stages.. )

IMHO, if you want to contrast CML with something, try CMOS.
CML outputs have TWO wires  and a swing that is a fraction of the supply, and multiple common model levels..
and typically match the driving impedance to the line impedance..  
CMOS outputs have a single wire, a rail to rail swing,  a minimal output impedance, and very high load impedance.
and a threshold level that is approx half the supply voltage.

Both of these terms can be applied to chip level design and board level.. and on chip level design the variety is quite large..
(30v CMOS (RCA 4000 series -> 65nm 0.8v standard cells and shrinking.. )

2 level SiGe npn based 40Ghz logic @ 10ma/gate -> 4 level nmos based 10GHz logic at 10- 1000ua /gate
 
Off soapbox

begin shameless self promotion
While the paper archives aren't up yet, If you read this far you might want to look at
"Verification of CML circuits used in PLL contexts with Verilog-AMS" in the 2006 archives at http://www.bmas-conf.org
jbd