I have a 3.3V analog PLL now and am thinking about replacing it with a low voltage PLL to reduce area.  However, I can think of a lot of potential design issues associated with low voltage PLL, such as higher clock jitter because of higher VCO gain, lower headroom for the chargepump circuit, potential gate leakage on the filter caps due to thinner gate ox, and so on. There seems more cons than pros that discourage me from pursuing going with a low voltage PLL.  Basically, I have to deal with more design issues and give up some jitter performance for smaller area.