Hi guys,

Can anyone familiar with the flicker noise calculation explain how to
set the lower frequency bound for the flicker noise? The theory I know
is that the lower frequency bound should be inversely proportional to
the cicuit ON time. Because of the random walk theory which gives rise to
the 1/f noise frequency spectrum, the longer the circuit ON time is,
the higher the flicker noise energy becomes. For example, people set an
ADC's conversion frequency as the lower bound in calculating the total
flicker noise. This approach is pretty vague and arbitrary to me. Any
rigorous analysis and theory behind this? I am designing an input buffer
for a sigma delta ADC.  I know chopping is one way to modulate the
flicker noise and remove it. But before embarking on that path, I want to
convince myself that I can't live with the flicker noise in the buffer.

I will really appreciate any feedback and opinion.

Best regards

Hi,

You should remember that the total noise power within a decade is constant for 1/f noise.
This means that there is only as much noise power in the band from 0.1Hz-1Hz as from
1uHz-10uHz.

Secondly, the lower frequency bound should be chosen on first order as the longest timeconstant
in your system where the ADC will be used. While 1 minute may be too long a lower bound if you
are designing the chip for a hearing aid, even 1 year may be too short if its a question of observing
astronomical objects

Regards
Vivek