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chviswanadh Junior Member Offline Posts: 18 Bangalore	how to simulate verilogA models Oct 05^th, 2006, 10:27pm Hello, I am new to verilogA. I want to know how to simulate the verilogA models at command promp. Secondly while using the cross function can we set a threhold limit other that 0 +1 and -1. Thanks chviswanadh
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Geoffrey_Coram

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Re: how to simulate verilogA models
Reply #1 - Oct 6^th, 2006, 3:44am

chviswanadh wrote on Oct 5^th, 2006, 10:27pm:

I am new to verilogA. I want to know how to simulate the verilogA models at command promp.

Which command prompt? (You can't mean the MS-DOS or unix command prompt.) What simulator are you using? Generally, you have to find the right syntax to add the Verilog-A model to your netlist, and then you use the simulator at the command prompt the way you did before.

Quote:

Secondly while using the cross function can we set a threhold limit other that 0 +1 and -1.

You're confusing the threshold limit and the direction argument. The threshold is always 0, but of course, if you want to detect V(clock) crossing 2.5 volts, then you write cross(V(clock) - 2.5, 0) so that you are detecting "V(clock) - 2.5" crossing 0. The +1, -1, 0 are to detect crossing from below to above, above to below, or either.

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chviswanadh

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Re: how to simulate verilogA models
Reply #2 - Oct 6^th, 2006, 7:34am

Hi Geoffrey,

Thanks for your reply.

So cant we simulate verilogA code at unix command prompt??? (as verilog models can be through ncverilog)
I am using Spectre simulator. How can we simulate verilogA models at command prompt through spectre simulator??

I was confused with the direction and threshold, now I understood how to use cross function

.

Thanks
chviswanadh

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bernd

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Re: how to simulate verilogA models
Reply #3 - Oct 6^th, 2006, 8:37am

Quote:

So cant we simulate verilogA code at unix command prompt??? (as verilog models can be through ncverilog)

You can't really like you are used from ncverilog.
You can simulate with VerilogAMS code form the command prompt
similar to NC-Verilog with Cadnence AMS Designer.
I don't know if this is also possible for Mentors ADVanceMS.

Quote:

I am using Spectre simulator.
How can we simulate verilogA models at command prompt through spectre simulator??

You have to have a netlist which includes the VerilogA models.
Something like this:
ahdl_include "/<pathToYourLibrary>/libName/cellName/veriloga/veriloga.va"

Then in principal you can simulate with Spectre
spectre <yourNetlist>

Try 'spectre -h' from the command line.

Just to satisfy my curiosity why do you want to simulate VerilogA form the
command line with Spectre?

Bernd

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chviswanadh

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Re: how to simulate verilogA models
Reply #4 - Oct 7^th, 2006, 3:15am

Hello Bernd,

Thanks for your reply.

Actually we have less number of licenses for ADE, So I thought if we have a way of simulating the verilogA models other than ADE.

That is why I asked how to do it in command prompt.

I have another question here, what are the other simulators we can use for simulating verilog models other than spectre.

chviswanadh

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Geoffrey_Coram

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Re: how to simulate verilogA models
Reply #5 - Oct 9^th, 2006, 6:14am

Bernd is right, you put the ahdl_include line in your netlist along with the instantiation of the element.

ahdl_include "mymos.va"

M1 (d g s b) mymos l=1u w=10u

where the file "mymos.va" includes the definition of the module "mymos"

chviswanadh wrote on Oct 7^th, 2006, 3:15am:

I have another question here, what are the other simulators we can use for simulating verilog models other than spectre.

Verilog-A models can be simulated in Spectre, HSpice, Eldo, Agilent ADS, Simucad/Silvaco SmartSpice, Xpedion's GoldenGate ... the list goes on. Some of these require a license for the extra feature.

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chviswanadh

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Re: how to simulate verilogA models
Reply #6 - Oct 12^th, 2006, 12:32am

Hi Geoffrey,

Thanks for your reply.

I would like to know whether I am doing the right way to simulate the behavioral models. So i am breifing what I am doing now.

I am making a cell view with verilogA editor and making a symbol out of that. Then I am using this symbol in the design where I need to use it.

But in the netlist generated from such designs I didnt see any statement like ahdl_include.

Is the way I am simulating the verilogA modes right??

Thanks
Chviswanadh

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Geoffrey_Coram Senior Fellow Offline Posts: 1998 Massachusetts, USA	Re: how to simulate verilogA models Reply #7 - Oct 12^th, 2006, 4:33am You should search this forum for posts about "stop views" I have a different way of generating the netlist ( not through ADE), so I don't know how to get the ahdl_include files in that way, but I'm pretty sure it has something to do with stop views. I thought you were trying to avoid using ADE ...
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chviswanadh Junior Member Offline Posts: 18 Bangalore	Re: how to simulate verilogA models Reply #8 - Oct 15^th, 2006, 3:38am Hi Geoffrey, Thanks for the reply I will look into that. Actually I am pretty new to VerilogA. So I am getting an idea of how to simulate them at the same time I want to avoid using ADE as well. Thanks chviswanadh
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