I currently use verilogA (in cadence 2006) to simulate a component with non static internal variable that I'd like to load/store (read/write from/to a file) corresponding to its instance (number or name, like I0,I1...), since the same component is replicated many times, I don't know if it's possible to write some verilog A code and how to get the instance name from the netlist ?

Thanks

There are also a bunch of % codes that only work when opening the file (something like %C.%r for the circuit and standard extension? %T? for the time code)
I don't know if they have been worked into the standard, but I couldn't use them on the Verilog-digital side back in 2002.

But it sounds like what you want might be better accomplished with a paramset or even a simple string parameter for the file name.
that way rather then specifiying the file per instance name, you can create all the variations of files and assign them to an instance when you put it in the schematic.
Of course in older versions of Cadence you wont be able to use string parameters
jbd

Verilog-A was based on 1364-1995 (the committee is presently updating it to 1364-2005), and that (digital) Verilog standard did not have $fread.  It did have $readmemb and $readmemh, so you could try those functions...