Geoffrey_Coram
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In digital Verilog, leaving a port (terminal) unconnected is well-defined; it's treated as an unknown when an input and as high-impedance when an output.
Since Verilog-A is derived from Verilog, it has to follow the same rules. It's a little strange when it iterfaces with Spice, though, because in Spice, terminals must be connected (generally - sometimes, as in BSIMSOI, there are extra terminals for self-heating that are connected conditionally on parameters).
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