I've download the verilog-a model of vco on designers-guide.
http://www.designers-guide.org/VerilogAMS/functional-blocks/vco/vco.vahttp://www.designers-guide.org/VerilogAMS/functional-blocks/vco/vco.scsI changed some vco parameter in spectre netlist (vco.scs)
for VCO1 in vco.va file
I specify vmin=0 vmax=3.3 fmin=1 fmax=2e9
and after I run the transient simulation, I found strange result during the frequency ramping process.
as shown below
when the input voltage is large than zero, vco starts to oscillator as voltage increase as expected.
but at some time, the vco seems to stop for a while (the gap). I don't know where comes this problem, but it does bring mistakes in my pll's lockin process.
Also the verilog-a vco model intends to let real variable 'phase' (also ploted in the snapshot) integral and modulos between -pi and +pi.
But the envelop of phase's waveform said it is not.
can anyone help me out? thanks in advance!