I have an on-chip amplifier followed by a Class-AB buffer driving an off-chip PNP in a feedback mode, providing a 3.3-to-1.8V regulated output. In my measurements the base of the PNP is railed to 3.3V on standy-mode and somehow have 180uA from emitter side (can PNP provide this current in cutoff region  :o). The base voltage moves to 2.5V when there is a large loading current. At both instances the collector is at 1.9V and emitter at 3.3V. Any suggestions on what is going on? In simulation everything seems ok at all corners even if I put a large input offset in the on-chip amplifier. Ideally I want the base voltage to be at 2.6V and collector at 1.8V in standy mode

Thanks for your reply.

I got a more sensible measurement today. Now my emitter sits at 3.3V, collector at 2.5V and base at 3.3V and no current flows! Seems like the feedback is not working properly. There might be something wrong with the connection on the PCB board ... still checking. One more thing, when I pull a large current from the collector the voltage pulls down to 1.9V and base move down to 2.6V.

Hmm ... but with or without the probe there is no current, the BJT is off. I have placed a 30pF and 1MOhms loading in the simulation so it shouldnt be a problem. Still puzzled why the feedback is railing the base to 3.3V in standby mode and move down to 2.5V when there is large load current. Basically the BJT is going from cutoff to active region so its bound to oscillate when I go from standy mode to normal mode. Ideally in simulation the BJT should be in active region and remain there regardless of the mode of operation. Also I have added 22uF capacitor at the collector to add a zero for stability.

uncle_ezra wrote on Oct 26^th, 2006, 12:58am:


it should say what it is on the back... but usually they're 10Mohm... and if you can tolerate 30pF, then make sure you are using short (<0.5m) probe leads, then there shouldn't be a capacitance problem. If you're unsure you should use an oscilloscope, which has defined input R and C (typically 1Mohm//10pF on x1).

I'm curious what your phase margin is between no load and large load.  I designed a linear voltage regulator before with mosfet driver and had to provide a dc path to ground as a minimum current load for loop stability reason. My phase margin decreases with lower current load.  

Another question I have is since there seems to be some discrepancies between simulation and reality, so I'm wondering if you included the bondwire and such between the chip and the bjt in your simulation.

Thanks for everyone's input. I found out that I needed a higher Q capacitor

Does anyone know how to design regulator for higher ESR? What changes should one make in order to cope with lower Q capacitor? I found out that using a small signal analysis can be misleading in regulator design because even for high ESR >5Ohms the small signal tells me that the circuit is stable but if you run a transient it oscillates  :o

Has anyone experienced probing an unstable regulator and then releasing to find out it is stable ?????  :o  Anyone can explain this phenomena? I am still talking abt the same regulator described above. Basically probing either the base or collector I see oscillation on the oscilloscope when I powerup but then somehow it disappears after probing it. Seems like after pertubing the regulator becomes stable, totally confused ???

I know the source is from the regulator. From the oscilloscope the output of the regulator is clean but maybe the harmonics are too small to be seen in an oscilloscope.