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question about PLL jitter (Read 788 times)

semitao Junior Member Offline Posts: 20	question about PLL jitter Nov 01^st, 2006, 7:08pm Hi,all. Who can tell me how to simulate the PLL jitter? When analyze the phase noise of VCO, we can use the Pnoise in spectre. I don't know how to analyse the noise from charge pump & PFD, anyone can help me? Thanks in advance.
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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: question about PLL jitter Reply #1 - Nov 2^nd, 2006, 8:00am Getting an accurate simulation of this is not an easy thing. First - Ring Oscillator VCO or LC VCO?
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semitao

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Re: question about PLL jitter
Reply #2 - Nov 2^nd, 2006, 9:03pm

Ring VCO
I am puzzled with how to select the charge pump current. As we know, the higher values of charge pump current lead to lower output phase noise. But the large current is limited by how large of capacitor values can be realized in the the loop filter implementation.
So, I have to decrease my pump current to get smaller capacitor, but I can't simulate the phase noise of detector to check the effect of new pump current. What can I do?

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hchanda Community Member Offline Posts: 33	Re: question about PLL jitter Reply #3 - Nov 2^nd, 2006, 11:24pm Why do you need to reduce the capacitor if you are increasing the chargepump current? I did not follow your explaination.
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semitao Junior Member Offline Posts: 20	Re: question about PLL jitter Reply #4 - Nov 5^th, 2006, 5:49pm Hi hchanda, I want to decrease the chargepump current to reduce my capacitor. my capacitor is 108pF, it's too large for my layout.
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