As we know, there is a trend these days for  RF IC design to move towards submicron processes due to cost. With the traditional analog/RF design topologies, it is more difficult to acheive any performance with lower process voltages (1-1.2V) and higher electrical leakage.  This is giving way to simpler analog circuits with more and more innovative digital circuits. For example, there is a trend for digital sampling circuits. VCOs are going to DCOs, PLLs to all digital ones, etc...What really are the design challeges with these new topologies and processes? Will these processes ever be good enough to really do traditional analog/RF?  Perhaps the challenges can be catagoried into designing and simulating circuits (for example with stocastic-like noise characteristics), process parasitics, transistor modeling, process variations, testing, other?  Is there any references or paper discussing these subjects in some detail? Or, does anyone have a good understanding of this to speak about it, especically from the design and simulation point-of-view?

thanks,

A lot of the RF and mixed signal world is better left at 0.18 or 0.13 geometry.

As you get into 90nm and smaller the issues with leakage, and matching start to affect the design architecture in a big way.

It is an evolution, a lot of us have ben riding the bandwagon since 5 micron bipolar.
Good engineers find ways to work with what they are given.