kidhyun
Junior Member
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Posts: 14
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Hi,
Pleae let me know how to pass parameters when I instantiate verilog-a module in hspice. For example, there is a resistor module in verilog-a. Then in hspice I have to do .hdl 'resistor.va' x1 a b resistor // when resistor is the module name
The how can I pass a parameter value (resistor value) here? Do I have to make seperate verilog-a module for each resistor with different resistance?
Thank You
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