Hi all,

i'm trying to simulate the output impedance of an NMOS transistor at 2.45 GHz. The DC solution in theory is roughly,

Rout = 1/lambda.IDS

my setup is like this,



As you can see, the current is fixed by the ideal current source at the source of the transistor. I used S-Parameter analysis and plotted Z11 in magnitude. Thus is contains both the real and imaginary component. I am using the 0.18 um process and the PDK i'm using has so far proven to be reliable enough.

Sweep           Dependence
-------            --------------
VGS              weak
IDC               weak
VDD              weak
L                   quite weak
Fingers          weak*
W                  Strong

So from the data i found that by far the biggest factor in determining the output impedance was the transistor width. Is this a well known phenomenon? I thought that at 2.45 GHz the transistor would still roughly follow the DC solution.

The strange thing is that when i ran a simulation of output impedance versus IDC for a full LNA, I found it to roughly follow the 1/IDC curve. So anybody know what i've been doing wrong or what's going on?

thanks,
Aaron

Hi Aaron,
Could you please share the answer as well?

thnx
eng

So do you short out I0 with a shunt ideal cap?  if so do you balance the vds/idc to ensure the source is at ground in a DC simulation to give you 600mV vds ?
I usually bias NM0 off a mirror to set the current, this way you know NM0 source is at ground always and zero degeneration or vbs exists, and you get the vds you put in V1 without having to juggle vgs as well.

yes you don't get 1:1 so i usually just sweep Ibias to the mirror to find the value i want in NM0...
also yes you can add a cap to the gate if you want a low impedance on the gate.... to match your vdc vgs drive you'll probably need it to match the results closely.