Hi,

I need to increase the lenght of a transistor in the design to about 6 times its current size. The current lenght is at the max allowed by the process. One way to do this is to put 6 transitors in series of the same W/L in series. This should result in W/(L*6).

As far as I know this is a valid implementation. The simulator however interprets this differently (of the 6 series transistors 5 of them will be in triode). Are any results different because of this? Do I have to look out for anything in such an implementation?

These transistors are being used for current mirrors and the two NCH loads of a diff-amp.

thanks in advance
A.

Hi Vivek,

Thanks for responding.

>>1. The model of the transistor used in schematic (6*L) may be different from the one you
>>actually have in physical implementation.

The physical implementation matches schematic drawing. The schematic also has 6 transistors in series (similar to layout). Is that what you are referring to here? All simulations are with series transistors as well.

The reason I ask this question is that I saw some odd behavior in simulations. I was using these transistors as loads for the first stage of a miller compensated two stage diff amp. This diff amp is a part of a bandgap reference. At a few corners, for transient sims, the amp rails to an impossible state (+ve input > -ve input, output railed to ground).

DC operating point and PM/GM/loop gain simulate fine. Nothing is borderline. This odd state shows up only in transient sims.

This happens only if the start-up circuit is connected (during start-up, the output is forced to ground). An external enable pulse is used to control the start-up circuit. The start-up circuit is off when the opamp is in the railed condition.  

Reducing the miller cap drastically doesnt force the opamp to oscillate either. Spice and spectre give me the same results.

Any ideas??

cheers,

Andy.

Hi Andy,

Could you please post the schematic? I think your problem may lie outside the amp itself.

ACWWong's suggestion of using a cascode is wise if you have the headroom for it, although I think
your amp is still fine. Possibly, there is some issue with your startup network.

Regards
Vivek

The practice of using series resistors to create the effect of larger channel length is common and approrpriate.

If you actually integrate Id over the the channel lengths:     ∫Id dy1 + ∫Id dy2  (where dy1 is the channel of one device and dy2 is another device, in series) they are actually equivalent to a single device of the summed up channel lengths.

i.e.  ∫Id dy1 + ∫Id dy2 = ∫Id dy_total

What you discover is that it is impossible to have more than one device, in a series string, that is in saturation, as it turns out the superior device in the series will always be the only device in saturations and the rest should be in linear ( I would bet that that is what your simulator is stating).  If anyone wants the math behind it I have it written down from an analysis I did several years ago.

So yes, it is a valid implementation and yes your simulator is simulating it correctly.  If you are still unsure, a perfectly valid way to test the theory is to simulate/plot the standard MOS I-V curves with Id versus Vds with Vgs swept, using your serie devices as a single transistor.  You should get reasonable plots.


I should also mention, that the macro device, if not bias correctly will show all devices in linear just as if a single device of that channel length (6*L) was in linear. So my comments are directed to the situation that the macro device is biased in saturation.

BGR picture attached. The circuit diagrams are turning out to be big. Do you have any suggestions to make them smaller? The opamp shown in bgr.png was attached with the earlier post.

In the bgrOpamp figure, the grounds seem disconnected in the circuit. They are not.

cheers,
Andy

Thanks  for the response.

The bulk connections are all implicitly (by naming the net) or explicitly tied to ground.

Sorry for the misleading schematic. It comes from multiple edits to opt in and opt out those series transistors (and not having a cleaned up snapshot of the schematic at home to post).

Oh yes the input transistors of the first stage is in subthreshold and so is M6. All current mirrors are in saturation.

I find that I see this problem even if I add a resistor of the order of 2M to these series transistors (4 series transistors + 2M resistor in series). The 2M is because thats what the gds of each of those triode transistors simulate to be. Just another data point for me.

thanks& regards,
andy

I am not sure, and I suppose you have checked this circuit throughout, but it sounds to me like the systematic offset is getting
out of hand at some corners, and this is driving the output to the rails.

I assume that you have sized the current sources so that you have equal current densities in the input stage mirror and the output stage device. If this is the case, then your output device is *not* matched to the composite series transistor device in the input stage, and the simulator (depending on the model you use...) may pick different model bins for each one of them. Both  the composite device and the output device behave the same (region of operation, etc) in some situations, but at some corners the predicted current for each is far enough apart  that the output rails. Since it goes to Vdd one knows that the ouput device is drawing less current than it should. Use a composite series device in the ouput stage and resimulate to check for this.

As already mentioned you will be boldly  pushing the foundry model where it has never gone before, so your design "as is" may actually work fine (long devices, not too narrow) ,... or not. Using the same unit device in the input and output at least gives you the comfort of meeting qualification tests, and if totally wrong then you'll have some interesting discussions later with the test engineer once the chip is back and on the bench.

Been there, btw, w/ something very similar.

Well, if you put two MOSFETs in series (gates connected together), the top FET needs at least a Vth drop to be on, so the bottom FET will have a drain voltage that is at least one Vth below its gate voltage; the bottom FET is not in saturation.

It's not too tricky to show this config behaves like a single MOSFET with W/(2*L).  Just set I1=I2 for the cases where the top is saturated or linear.

I believe it's always better to use the same L, firstly because the nominal Vth is the same, and also because each L sees the same diffusion variation (i.e. Leff = L - Ldiff - Xd).  Right... 6*(L-0.2) gives a desired ratio, vs. 6L-0.2 (i.e. not 6 times the length of a single FET).

For those series transistors, the body effect of course is going to come into play and reduce current drive.