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Simulating ESD discharge in Verilog (Read 3070 times)

Dimitri New Member Offline Posts: 1 Leuven, Belgium	Simulating ESD discharge in Verilog Nov 14^th, 2006, 3:24am Hi, I want to implement an ESD discharge in VerilogA Therefor I want to have an initial condition on a capacitance ( e.g. 1 kV) How do I state this in Verilog ? @(initial_step) ? Regards,
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Pavel Senior Member Offline Posts: 174 Lausanne/Switzerland	Re: Simulating ESD discharge in Verilog Reply #1 - Nov 16^th, 2006, 1:49am There is article "Compact Modeling of On-Chip ESD Protection Devices Using Verilog-A" IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 6, JUNE 2006 that explain ESD modelling in Verilog-A. Unfortunately I can't attach it as its size is more than 500k. Regards. Pavel
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Geoffrey_Coram Senior Fellow Offline Posts: 1998 Massachusetts, USA	Re: Simulating ESD discharge in Verilog Reply #2 - Nov 16^th, 2006, 11:34am Dimitri wrote on Nov 14^th, 2006, 3:24am: How do I state this in Verilog ? @(initial_step) ? No. Probably with analysis("ic").
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