Geoffrey_Coram
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I don't think you meant string parameter. I believe your question should have been: is it legal to use a string literal as an actual argument for a macro? And the answer is: yes.
For example, if you define this: `define mydebug(x) $strobe("DEBUG: ", x)
then you should be able to call it with the string literal "line 101"
`mydebug("line 101")
If you really were asking about string parameters, they were added to Verilog-AMS LRM 2.2, and maybe that's why you can't find them where you are looking; they're not supported by all simulators yet. I'm not exactly sure what your question is; are you trying to override an instance parameter? Or trying to pass a string parameter as the argument to a macro? Using the definition above, if you also have
parameter string myname = "X1";
you should be able to
`mydebug(myname)
-Geoffrey
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