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jyu06

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clock buffer jitter simulation
Dec 13^th, 2006, 9:54pm

Hi, All,
I am using spectreRF to simulate clock jitter of a clock buffer to drive ADC.
We have a question for the setup of pnoise simulation:
what is the start frequency and end freq we should use to integrate the pnoise to obtain clock jitter?
Based on my understanding, the end point may be fs/2 or fs, depending on the pnoise spectrum is one-sided or two-sided. In addition, the start point sometime is important if low frequency phase noise is high. Some people suggested fs/N, where N is the total number of points to do FFT calculation, e.g. 32k.
Could you give us some more explanation or relavant references?
Regards,
James

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smlogan

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Re: clock buffer jitter simulation
Reply #1 - Dec 31^st, 2006, 8:10pm

HI jyu06,

The maximum and minimum frequencies to use to compute clock jitter are really application dependent - but I can try to add a few cents ...

The maximum frequency limit is either set by a standard (for example, SONET/SDH transmission channel or Fibre Channel requirements), the capability of a measurement instrument or limited by available data.

The maximum jiitter frequency limit is the baud rate (for data) or clock rate divided by 2. Intuititely, for a clock signal, one cannot detect a jitter frequency that occurs more than once every clock cycle. For example, if every even clock pulse has a width delta_t1 and every odd clock signal has a width delta_t2, then the period of the jitter is 2 clock periods. With a clock period Tc (and hence frequency fc = 1/Tc), the resulting maximum jitter period is 2Tc - or a maximum jitter frequency of (1/2)*fc.

The minimum jitter frequency, in your case I think, is set by the minimum frequency that the post-processing of your resulting digital data is sensitive too (I'm assuming aliasing is not an issue. If aliasing is an issue - or you are doing band-limited sampling, folding of the resulting spectrum may cause some lower freqeuncy jitter components to end up "in band"). For example. suppose your digital data is fed to a bandpass filter. Then the amount of jitter that will significantly impact the signal within the bandpass filter is limited to the bandpass filter upper and lower cut-off frequencies.

Hence, there is no limit to the lower frequency, in general.

I'm not sure if I've explained my thoughts well enough. Let me know if I've managed to clarify anything or if there are any more specifics about the application that might help me better understand your lower integration limit a bit better.

Shawn

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Shawn

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jyu06

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Re: clock buffer jitter simulation
Reply #2 - Jan 23^rd, 2007, 9:14pm

Hi, Shawn,
Thank you for the explanation.
I have several questions on this issue. The following is my understanding.
Suppose I have a square wave clock for sampling. The noisy square wave(with jitter) can be decomposed to many sinusoids, each of which may
have noise. So the variation of trigger time is then determined by the phase noise of each of this harmonics.
PSS tool will help us to calculate the effect of phase noise of these harmonics and do summation. I don't know if the final Pnoise spectrum is two-sided or one-sided, (integral from -fs/2 to fs/2 (for two sided case) is equal to integral from 0 to fs/2 (for one-sided case) ).
For our case, aliasing is not a issue and lower limit is set by DFT.
Thank you,
James

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smlogan

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Re: clock buffer jitter simulation
Reply #3 - Feb 4^th, 2007, 9:01pm

Hi jyu06,

If you use the Cadence function phaseNoise(), I believe it normalizes the result to the carrier and then computes L(f). This is, by definition 1/1 * Sv(F). Hence, when computing the rms jitter over a frequency range, a factor of 2 is necessary to account for both sides of the spectrum.

Hope that helps!

Shawn

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Shawn

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Ken Kundert

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Re: clock buffer jitter simulation
Reply #4 - Mar 12^th, 2007, 5:27pm

Since you are interested in jitter, you would sample the noise at the threshold crossing and divide by the slew rate at that point. Thus, you are interested in the power in a discrete-time sampled-data sequence. If the sample rate is f_s, then the spectrum of this sequence is periodic in the frequency domain with period f_s. To get the total power of the sequence, you would integrate power spectral density from f=0 to f_s/2.

-Ken

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jyu06

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Re: clock buffer jitter simulation
Reply #5 - Mar 19^th, 2007, 10:43pm

Hi, Ken,
Thanks for the reply.
When I plotted the jitter spectrum (in cadence ADE), the y-axis unit is sec/sqrt(Hz). Just wonder if it means
the noise voltage's been normalized to jitter according to rise/fall crossing edge slew rate?
When I used matlab to do fft on x(k) k from 1 to N. I got X(K), K from 1 to N.
I sum x(k) from 1 to N to get the totoal power in time domain, and I do need to sum X(K) from 1 to N to
get the equal power in frequency domain, which is corresponding to 0 to fs, although spectrum of 0-fs/2 and
that of fs to fs/2 is the same.
So I assume cadence tool already add the power from fs/2 to fs to 0-fs/2, so I only need to integrate from 0 to fs/2 to get the
total power.
Thanks,
james

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M.C. New Member Offline Posts: 3	Re: clock buffer jitter simulation Reply #6 - Apr 8^th, 2007, 7:56pm Hi Ken, From what I've read, spectreRF allows us to find the PSD of the noise at a certain time instant in a periodic signal (such as the clock buffer used in this example). Do you know if hspiceRF allows us to do the same? Thanks, M.
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